Operational Amplifiers Gate Questions | Analog Circuits

Question 1
For the operational amplifier circuit shown, the output saturation voltages are ±15V. The upper and lower threshold voltages for the circuit are, respectively.
A
+5V and -5V
B
+7V and -3V
C
+3V and -7V
D
+3V and -3V
Question 1 Explanation: 
 
Question 2
An ideal op-amp has voltage sources V1, V3, V5, ..., VN-1 connected to the non-inverting input and V2,V4, V6, ..., VN connected to the inverting input as shown in the figure below (+Vcc= 15 volt,—Vcc= —15 volt). The voltages V1, V2, V3, V4, V5, V6,... are 1, — 1/2, 1/3, —1/4, 1/5, —1/6,... volt, respectively. As N approaches infinity, the output voltage (in volt) is
A
Fill in the Blank Type Question
Question 2 Explanation: 
Question 3
For the NMOSFET in the circuit shown, the threshold voltage is Vth, where Vth > 0. The source voltage VSS is varied from 0 to VDD. Neglecting the channel length modulation, the drain current ID as a function of VSS is represented by
A
Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image199.jpg
B
Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image200.jpg
C
Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image201.jpg
D
Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image202.jpg
Question 3 Explanation: 


Hence MOS transistor is in saturation.
In saturation,
D
As Vss increases ID decreases (Not linearly because square factor)
Hence option A. is correct.
Question 4
In the op-amp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage Vo to +5 V or -5V. The switch S is initially closed and is opened at time t=0 The time t = t1 (in seconds) at which Vo changes state is ____
A
Fill in the Blank Type Question
Question 4 Explanation: 
Question 5
An op-amp has a finite open loop voltage gain of 100. Its input offset voltage Vios(= +5 mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects.
Vinput Is 25 mV

The output voltage (in millivolts) is _____
A
Fill in the Blank Type Question
Question 5 Explanation: 
The gain of the practical op-amp
Question 6
In the circuit shown, assume that the opamp is ideal. If the gain (v0 / vin) is –12, the value of R (in kΩ) is _____.
A
Fill in the Blank Type Question
Question 6 Explanation: 

Given

Question 7
In the ac equivalent circuit shown in the figure, if iin is the input current and RF is very large, the type of feedback is
A
voltage-voltage feedback
B
voltage-current feedback
C
current-voltage feedback
D
current-current feedback
Question 7 Explanation: 
Output sample is voltage and is added to the input current.
Since, feedback is diectly connected to output so the sampling is voltage and mixing is current type.
∴ It is voltage – shunt negative feedback i.e., voltage-current negative feedback
Question 8
The feedback topology in the amplifier circuit (the base bias circuit is not shown for simplicity) in the figure is
A
Voltage shunt feedback
B
Current series feedback
C
Current shunt feedback
D
Voltage series feedback
Question 8 Explanation: 
By opening the output feedback signed becomes zero. Hence it is current sampling. As the feedback signal vf is subtracted from the signal same vs it is series mixing.
Question 9
An analog voltage in the range 0 to 8 V is divided in 16 equal intervals for conversion to 4-bit digital output. The maximum quantization error (in V) is _________________
A
0.20
B
0.25
C
0.30
D
0.40
Question 9 Explanation: 
Dynamic range or voltage range = 0 to 8 V
Number of levels = 16
Maximum quantization error Qe =stepsize(Δ)/2
Where Δ = Dynamic Range/L = 8/24 =8/16=0.5
Therefore Maximum quantization error = 0.5/2 =0.25 V
Question 10
The circuit shown is a
A
Low pass filter with
B
High pass filters with
C
Low pass filter with
D
High pass filter with
Question 10 Explanation: 
T(s) =
T(s) =
It is the transfer function of high pass filter with cutoff frequency ω = rad/sec
Question 11
The voltage gain Av of the circuit shown below is
A
B
C
D
Question 11 Explanation: 







Apply Miller's theorem to 100 k resistor





Question 12
For the same network, with 6 V dc connected at port A, 1 Ω connected at port B draws 7/3A. If 8 V dc is connected to port A. the open circuit voltage at port B is
A
6 V
B
7 V
C
8 V
D
9 V
Question 12 Explanation: 
There are 12 questions to complete.

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