Electronic Devices and Circuits | Subject Wise

Electronic Devices and Circuits subject wise

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Question 1

The value of the integral

is equal to __________.

A	Fill in the Blank Type Question

Discuss GATE EC 2019 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 1 Explanation:

Question 2

Which one of the following options describes correctly the equilibrium band diagram at T = 300 K of a Silicon pnn⁺p⁺⁺ configuration shown in the figure?

A
B
C
D

Discuss GATE EC 2019 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 2 Explanation:

Question 3

The correct circuit representation of the structure shown in the figure is

A
B
C
D

Discuss GATE EC 2019 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 3 Explanation:

Option A is correct Answer
-> As per the Question Structure shown is fabrication of npn transistor
-> Emitter highly doped (n⁺⁺)
-> Base lightly doped (p⁺)
-> Collector (n⁺⁺)
-> CB junction (n⁺⁺ – p⁺ junction)

Question 4

The figure shows the high-frequency C-V curve of a MOS capacitor (at T = 300 K) with Φ_ms = 0 V and no oxide charges. The flat-band, inversion, and accumulation conditions are represented, respectively, by the points

A	Q, R, P
B	Q, P, R
C	R, P, Q
D	P, Q, R

Discuss GATE EC 2019 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 4 Explanation:

Given C-V characteristics of MOS capacitor with p-type substrate for high frequencies.
Point-P possible in accumulation mode
Point-Q possible in flat band mode
Point-R possible in inversion mode
hence, option A is correct one

Question 5

In an ideal pn junction with an ideality factor of 1 at T = 300 Km the magnitude of the reverse-bias voltage required to reach 75% of its reverse saturation current, rounded off to 2 decimal places, is __________ mV.

[k = 1.38 × 10^-23 JK^-1, h = 6.625 × 10^-34 J-s, q = 1.602 × 10^-19 C]

A	Fill in the Blank Type Question

Discuss GATE EC 2019 Electronic Devices and Circuits Diodes and Its Applications

Question 5 Explanation:

Question 6

In the circuits shown, the threshold voltage of each nMOS transistor is 0.6 V. Ignoring the effect of channel length modulation and body bias, the values of Vout 1 and Vout 2, respectively, in volts, are

A	2.4 and 2.4
B	1.8 and 1.2
C	1.8 and 2.4
D	2.4 and 1.2

Discuss GATE EC 2019 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 6 Explanation:

Question 7

The quantum efficiency (η) and responsivity (R) at wavelength λ (in μm) in a p-i-n photodetector are related by

A
B
C
D

Discuss GATE EC 2019 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 7 Explanation:

Question 8

A bar of Gallium Arsenide (GaAs) is doped with Silicon such that the Silicon atoms occupy Gallium and Arsenic sites in the GaAs crystal. Which one of the following statement is true?

A	Silicon atoms act as p-type dopants in Arsenic sites and n-type dopants in Gallium sites
B	Silicon atoms act as n-type dopants in Arsenic sites and p-type dopants in Gallium sites
C	Silicon atoms act as p-type dopants in Arsenic as well as Gallium sites
D	Silicon atoms act as n-type dopants in Arsenic as well as Gallium sites

Discuss GATE EC 2017 Set 1 Electronic Devices and Circuits Basics of Semiconductors

Question 8 Explanation:

->Substituting a Gallium site by a si atom produces a free electron so n-type
->Substituting an Arsenic site by a si atom produces a hole
so p-type.

Question 9

An n⁺-n Silicon device is fabricated with uniform and non-degenerate donor doping concentrations of N_D1=1×10¹⁸ cm^-³ and N_D2= 1×10¹⁵ cm^-³ corresponding to the n⁺ and n regions respectively. At the operational temperature T, assume complete impurity ionization, kT/q = 25 mV, and intrinsic carrier concentration to be n_i= 1×10¹⁰ cm^-³. What is the magnitude of the built-in potential of this device?

A	0.748 V
B	0.460 V
C	0.288 V
D	0.173 V

Discuss GATE EC 2017 Set 1 Electronic Devices and Circuits Basics of Semiconductors

Question 9 Explanation:

Question 10

For a narrow base PNP BJT, the excess minority carrier concentration (∇n_Efor emitter, ∇p_Bfor base. ∇n_C for collector) normalized to equilibrium minority carrier concentration ( n_E0 for emitter, p_B0 for base, n_C0 for collector) in the quasi-neutral emitter, base and collector regions are shown below. Which one of the following biasing modes is the transistor operating in?

A	Forward active
B	Saturation
C	Inverse active
D	Cutoff

Discuss GATE EC 2017 Set 1 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 10 Explanation:

As per the change carrier profile, base – to – emitter junction is reverse bias and base to collector junction is forward bias,
so it works in Inverse active.

Question 11

The Miller effect in the context of a Common Emitter amplifier explains

A	an increase in the low-frequency cutoff frequency
B	an increase in the high-frequency cutoff frequency
C	a decrease in the low-frequency cutoff frequency
D	a decrease in the high-frequency cutoff frequency

Discuss GATE EC 2017 Set 1 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 11 Explanation:

Due to miller effect the effective input Capacitance seen through the base terminal will increase which in turn reduces the higher cutoff frequency

Question 12

Two identical nMOS transistors M₁ and M₂ are connected as shown below. The circuit is used as an amplifier with the input connected between G and S terminals and the output taken between D and S terminals, V_bias and V_D are so adjusted that both transistors are in saturation. The transconductance of this combination is defined as

while the output resistance is

where i_D is the current flowing into the drain of M₂. Let g_m1 , g_m2 be the transconductances and r_o1, r_o2 be the output resistance of transistors M₁ and M₂ respectively

Which of the following statements about estimates for g_m and r_o is correct?

A	and
B	and
C	and
D	and

Discuss GATE EC 2018 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 12 Explanation:

Question 13

There are two photolithography systems: one with light source of wavelength λ₁ = 156 nm (System 1) and another with a light source of wavelength λ₂ = 325 nm (System 2). Both photolithography systems are otherwise identical. If the minimum feature sizes that can be realized using System 1 and System 2 are L_min1 and L_min2 respectively, the ratio L_min1/L_min2 (correct to two decimal places) is ____________

A	Fill in the Blank Type Question

Discuss GATE EC 2018 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 13 Explanation:

Question 14

A p-n step junction diode with a contact potential of 0.65 V has a depletion width of 1μm at equilibrium. The forward voltage (in volts, correct to two decimal places) at which this width reduces to 0.6μm is _________.

A	Fill in the Blank Type Question

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Question 14 Explanation:

Formula for Width of depletion region in a pn junction, and from that relation between width and voltage can be directly applied to get the answer as follows,

Question 15

A junction is made between p^-Si with doping density N_A1 = 10¹⁵ cm^-3 and p Si with doping density N_A2 =10¹⁷cm^-3.

Given: Boltzmann constant k= 1.38 x 10^-23J.K^-1 , electronic charge q= 1.6 x 10^-19 C.

Assume 100% acceptor ionization.

At room temperature (T= 300K), the magnitude of the built-in potential (in volts, correct to two decimal places) across this junction will be ____________.

A	Fill in the Blank Type Question

Discuss GATE EC 2018 Electronic Devices and Circuits Basics of Semiconductors

Question 15 Explanation:

Question 16

In the circuit shown below, the (W/L) value for M₂ is twice that for M_1. The two NMOS transistors are otherwise identical. The threshold voltage V_T for both transistors is 1.0 V. Note that V_GS for M₂ must be > 1.0 V.

Current through the nMOS transistors can be modeled as

for

The voltage (in volts, accurate to two decimal places) at V_x is _______.

A	Fill in the Blank Type Question

Discuss GATE EC 2018 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 16 Explanation:

Question 17

A solar cell of area 1.0 cm² , operating at 1.0 sun intensity, has a short circuit current of 20 mA, and an open circuit voltage of 0.65 V. Assuming room temperature operation and thermal equivalent voltage of 26 mV, the open circuit voltage (in volts, correct to two decimal places) at 0.2 sun intensity is __________.

A	Fill in the Blank Type Question

Discuss GATE EC 2018 Electronic Devices and Circuits Optical and Semiconductor Materials

Question 17 Explanation:

Question 18

Red (R), Green (G) and Blue (B) Light Emitting Diodes (LEDs) were fabricated using –n junctions of three different inorganic semiconductors having different band-gaps. The built-in voltages of red, green and blue diodes are V_R, V_G and V_B respectively. Assume donor and acceptor doping to be the same (N_A and N_D respectively) in the p and n sides of all the three diodes. Which one of the following relationships about the built-in voltages is TRUE?

A	V_R> V_G >V_B
B	V_R <V_G< V_B
C	V_R= V_G = V_B
D	V_R> V_G < V_B

Discuss GATE EC 2018 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 18 Explanation:

->For LED and emitting lights if Red, Blue and Green colours, doping concentration on both sides are equal.

->We know that energy band gap and built in potential of a p-n junction is inversely proportional to wavelength, i.e.

Question 19

An npn bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base – collector junction is increased, then

A	the effective base width increases and common – emitter current gain increases
B	the effective base width increases and common – emitter current gain decreases
C	the effective base width decreases and common – emitter current gain increases
D	the effective base width decreases and common – emitter current gain decreases

Discuss GATE EC 2017 Set 2 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 19 Explanation:

"If the reverse bias voltage across the base collector junction is increased, then their effective base width will decrease and collector current will increase, therefore their common-emitter current gain increases."

If reverse bias across base collector junction will increases, then
(i) Depletion width across base collector junction will increase.
(ii) Effective base width will decrease.
(iii) Recombination of carrier in base region will decrease.
(iv) Common emitter current gain ( β = I_C / I_B) will increase

Question 20

Consider an n-channel MOSFET having width W, length L, electron mobility in the channel
µ_n and oxide capacitance per unit area C_ox. If gate-to-source voltage V_GS=0.7V, drain-to- source voltage V_DS=0.1V, ( µ_nC_ox) =100 µA/V², threshold voltage V_TH=0.3V and (W/L) =50, then the transconductance g_m (in mA/V) is______

A	Fill in the Blank Type Question

Discuss GATE EC 2017 Set 2 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 20 Explanation:

Given
V_GS=0.7V

Answer Range : (0.45 to 0.55)

Question 21

A MOS capacitor is fabricated on p-type Si (silicon) where the metal work function is 4.1 eV and electron affinity of Si is 4.0 eV. E_C-F_F=0.9 eV, where E_C and E_F are the conduction band minimum and the Fermi energy levels of Si, respectively. Oxide ∈_r =3.9, ∈₀=8.85 X 10^-14 F/cm. oxide thickness t_ox=0.1 μm and electronic charge
q= 1.6 X 10^-19 C. If the measured flat band voltage of the capacitor is -1V, then the magnitude of the fixed charge at the oxide-semiconductor interface, in nC/cm², is

A	Fill in the Blank Type Question

Discuss GATE EC 2017 Set 2 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 21 Explanation:

Answer Range : (6.85 to 6.95)

Question 22

For a particular intensity of incident light on a silicon pn junction solar cell, the photocurrent density (J_L) is 2.5 mA/cm² and the open-circuit voltage (V_OC) is 0.451 V. Consider thermal voltage (V_T) to be 25mV. If the intensity of the incident light is increased by 20 times, assuming that the temperature remains unchanged. V_oc (in volts) will be__________

A	Fill in the Blank Type Question

Discuss GATE EC 2017 Set 2 Electronic Devices and Circuits Basics of Semiconductors

Question 22 Explanation:

Question 23

An abrupt pn junction (located at x = 0) is uniformly doped on both p and n sides. The width of the depletion region is W and the electric field variation in the x-direction is E(x). Which of the following figures represents the electric field profile near the pn junction?

A
B
C
D

Discuss GATE EC 2017 Set 2 Electronic Devices and Circuits Carrier Transport

Question 23 Explanation:

->IF Left side is p-region and right side is n-region then electric field triangle will be down warded
->If Left side is n-region and right side is p-region, then electric field triangle will be upward.

Question 24

Assuming that transistors M1 and M2 are identical and have a threshold voltage of 1V, the state of transistors M1 and M2 are respectively.
2.45.JPG

A	Saturation, Saturation
B	Linear, Linear
C	Linear, Saturation
D	Saturation, Linear

Discuss GATE EC 2017 Set 2 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 24 Explanation:

then transistor is working in saturation region.
So, For transistor M₂

Assume that M1 is working in saturation, so that

Now, for M1, transistor to work in saturation

but it is not satisfied by M1 transistor and

so, transistor M1 is ON but working in linear region.

Question 25

A small percentage of impurity is added to an intrinsic semiconductor at 300 K. Which one of the following statements is true for the energy band diagram shown in the following figure?

A	Intrinsic semiconductor doped with pentavalent atoms to form n-type semiconductor
B	Intrinsic semiconductor doped with trivalent atoms to form n-type semiconductor
C	Intrinsic semiconductor doped with pentavalent atoms to form p-type semiconductor
D	Intrinsic semiconductor doped with trivalent atoms to form p-type semiconductor

Discuss GATE EC 2016 Set 1 Electronic Devices and Circuits Basics of Semiconductors

Question 25 Explanation:

Pentavalent impurity when introduced in intrinsic semiconductor then a new diecrete energy level called Donor energy level is created just below the conduction band

Question 26

Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET):
P: As channel length reduces, OFF-state current increases.
Q: As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.
Which of the above statements are INCORRECT?

A	P and Q
B	P and S
C	Q and R
D	R and S

Discuss GATE EC 2016 Set 1 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 26 Explanation:

P : TRUE, As channel Length reduces, off state current increases
Q: FALSE, As channel length reduces, output resistance reduces
R: FALSE: As channel length reduces, threshold voltage reduces
S: TRUE : As Channel reduces, ON current increases

If the channel length reduces, then threshold voltage also changes.

So option C is matching.

Question 27

Consider a silicon p-n junction with a uniform acceptor doping concentration of 10¹⁷ cm^-3 on the p- side and a uniform donor doping concentration of 1016 cm-ion the n-side. No external voltage is applied to the diode. Given: kT/q = 26 mV,

The charge per unit junction area (nC cm-2) in the depletion region on the p-side is

A	Fill in the Blank Type Question

Discuss GATE EC 2016 Set 1 Electronic Devices and Circuits Diodes and Its Applications

Question 27 Explanation:

Since, there are -ve charges in depletion region of p-type.
Therefore, answer is -4.836 nC-cm^-2

Question 28

Consider an n-channel metal oxide semiconductor field effect transistor (MOSFET) with a gate-to source voltage of 1.8 V. Assume that (W/L) = 4, μ_N C_OX= 70 x 10^-6AV^-2, the threshold voltage is 0.3V, and the channel length modulation parameter is 0.09 V^-1. In the saturation region, the drain conductance (in micro siemens) is _____.

A	Fill in the Blank Type Question

Discuss GATE EC 2016 Set 1 Electronic Devices and Circuits Basics of Semiconductors

Question 28 Explanation:

Question 29

Consider a silicon sample at T=300K, with a uniform donor density

illuminated uniformly such that the optical generation rate is

throughout the sample. The incident radiation is turned off at t=0. Assume low-level injection to be valid and ignore surface effects. The carrier lifetimes are

The hole concentration at t = 0 and the hole concentration at t = 0.3ms, respectively, are

A
B
C
D

Discuss GATE EC 2016 Set 1 Electronic Devices and Circuits Carrier Transport

Question 29 Explanation:

Question 30

A p-i-n photodiode of responsivity 0.8A/W is connected to the inverting input of an ideal op- amp as shown in the figure, +V_cc = 15 V, —V_cc = —15V, Load resistor

. If

Of power is incident on the photodiode, then the modulus of value of the photocurrent (in

) through the load is _____.

A	Fill in the Blank Type Question

Discuss GATE EC 2016 Set 1 Electronic Devices and Circuits Diodes and Its Applications

Question 30 Explanation:

Question 31

A region of negative differential resistance is observed in the current voltage characteristics of a silicon PN junction if

A	both the P-region and the N-region are heavily doped
B	the N-region is heavily doped compared to the P-region
C	the P-region is heavily doped compared to the N-region
D	an intrinsic silicon region is inserted between the P-region and the N-region

Discuss GATE EC 2015 Set 1 Electronic Devices and Circuits Diodes and Its Applications

Question 31 Explanation:

A region of negative differential resistance is observed in the current voltage characteristics of a silicon PN junction if both the P-region and the N-region are heavily doped.
Under normal forward bias operation as voltage begins to increase, electrons at first tunnel through the very narrow p-n junction barrier and fill electron states in the conduction band on the n-side, which becomes aligned with empty valence band hole states on the p-side of the p-n junction. As voltage increases further, these states become increasingly misaligned and the current drops. This is called negative resistance becomes current decreases with increasing voltage. p-n diode with high doping on both sides is called tunnel diode. Hence, the correct option is (A).

Question 32

A silicon sample is uniformly doped with donor type impurities with a concentration of 10¹⁶ /cm³. The electron and hole mobilities in the sample are 1200 cm²/V-s and 400 cm² /V-s respectively.
Assume complete ionization of impurities. The charge of an electron is 1.6 × 10^–19 C. The resistivity of the sample (in Ω-cm) is _________.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 1 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 32 Explanation:

$Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image050.png$

$Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image052.png$

Question 33

The built-in potential of an abrupt p-n junction is 0.75 V. If its junction capacitance (C_J) at a reverse bias (V_R) of 1.25 V is 5 pF, the value of C_J (in pF) when V_R = 7.25 V is________.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 1 Electronic Devices and Circuits Diodes and Its Applications

Question 33 Explanation:

Question 34

For a silicon diode with long P and N regions, the acceptor and donor impurity concentrations are 1 x 10¹⁷ cm^–3 and 1 × 10¹⁵ cm^–3, respectively. The lifetimes of electrons in P region and holes in N region are both 100 µs. The electron and hole diffusion coefficients are 49 cm²/s and 36 cm²/s, respectively. Assume kT/q = 26 mV, the intrinsic carrier concentration is 1× 10¹⁰ cm^–3, and q = 1.6 × 10^–19 C. When a forward voltage of 208 mV is applied across the diode, the hole current density (in nA/cm²) injected from P region to N region is ______.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 1 Electronic Devices and Circuits Diodes and Its Applications

Question 34 Explanation:

The hole current density injected from P region to N region is given by
$Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image180.png$
Where,
Q = charge on electron
n_i = Intrinsic carrier concentration in silicon
N_D = Donor doping
D_P = Hole diffusion coefficient
L_p = Mean diffusion length of hole
V_FB = Forward voltage applied across diode
V_T = kT/q = 26 mV
$Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image181.png$
$Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-1_files\image182.png$
Using the above values, we get hole current density injected from P region to N region is = 28.617 nA/cm²
by substitute the values in the above equation

Question 35

The Ebers-Moll model of a BJT is valid

A	only in active mode
B	only in active and saturation modes
C	only in active and cut-off modes
D	in active, saturation and cut-off modes

Discuss GATE EC 2016 Set 2 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 35 Explanation:

Ebers Moll model is the classical model of BJT. This model is based on interacting diode junctions and is applicable to all the transistor operating modes

Question 36

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

A	Widths of PMOS transistors should be doubled, while widths of NMOS transistors should be halved.
B	Widths of PMOS transistors should be doubled, while widths of NMOS transistors should not be changed.
C	Widths of PMOS transistors should be halved, while widths of NMOS transistors should not be changed.
D	Widths of PMOS transistors should be unchanged, while widths of NMOS transistors should be halved.

Discuss GATE EC 2016 Set 2 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 36 Explanation:

Width of PMOS transistors should be doubled. while width of NMOS transistors should not be changed, because NMOS transistors are in parallel. If anyone transistor ON, output goes to LOW.

Question 37

A voltage VG is applied across a MOS capacitor with metal gate and p-type silicon substrate at T = 300K. The inversion carrier density (in number of carriers per unit area) for V_G = 0.8 V is 2 x10¹¹cm^-2. For V_G = 1.3V, the inversion carrier density is 4x10¹¹cm^-2. What is the value of the inversion carrier density for V_G = 1.8 V?

A	4.5 x10¹¹cm^-2
B	6.0 x10¹¹cm^-2
C	7.2x x10¹¹cm^-2
D	8.4 x10¹¹cm^-2

Discuss GATE EC 2016 Set 2 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 37 Explanation:

Question 38

Consider avalanche breakdown in a silicon p⁺n junction. The n-region is uniformly doped with a donor density N_D. Assume that breakdown occurs when the magnitude of the electric field at any point in the device becomes equal to the critical field E_crit. Assume E_crit to be independent of N_D. If the built-in voltage of the

junction is much smaller than the breakdown voltage, V_BR, the relationship between

and

is given by

A	= not constant
B	= constant
C	= constant
D	= constant

Discuss GATE EC 2016 Set 2 Electronic Devices and Circuits Diodes and Its Applications

Question 38 Explanation:

Question 39

Consider a region of silicon device of electrons and holes, with an ionized donor density of

. The electric field at x = 0 is 0 V/cm and the electric field at x = L is 50 kV/cm in the positive x direction. Assume that the electric field is zero in the y and z directions at all points.

Given q =1.6 x10^-19 coulomb,

for silicon, the value of L in nm is_____

A	Fill in the Blank Type Question

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Question 39 Explanation:

Question 40

Consider a long-channel NMOS transistor with source and body connected together. Assume that the electron mobility is independent of V_GS, and V_DS. Given,
g_m= 0.5 μA/ V for V_DS= 50 mV and V_GS= 2V,
g_{d =}8 μA/ V _forV_DS = 0 mV and V_GS= 2V_,
The threshold voltage (in volts) of the transistor is ______

A	Fill in the Blank Type Question

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Question 40 Explanation:

Question 41

The I-V characteristics of three types of diodes at the room temperature, made of semiconductors X, Y and Z, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If EgX, EgY and EgZ are the band gaps of X, Y and Z, respectively, then
3.10.JPG

A
B
C
D	no relationship among these band gaps exists

Discuss GATE EC 2016 Set 3 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 41 Explanation:

Question 42

The figure shows the I-V characteristics of a solar cell illuminated uniformly with solar light of power

. The solar cell has an area of

and a fill factor of 0.7. The maximum efficiency (in %) of the device is ______.

A	Fill in the Blank Type Question

Discuss GATE EC 2016 Set 3 Electronic Devices and Circuits Diodes and Its Applications

Question 42 Explanation:

Question 43

A triangle in the xy-plane is bounded by the straight lines 2x = 3y, y = 0 and x = 3. The volume above the triangle and under the plane x + y + z = 6 is ______

A	Fill in the Blank Type Question

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Question 43 Explanation:

Question 44

The injected excess electron concentration profile in the base region of an npn BJT, biased in the active region, is linear, as shown in the figure. If the area of the emitter-base junction is 0.001

in the base region and depletion layer widths are negligible, then the collector current Ic (in mA). at room temperature is __________

(Given: thermal voltage VT = 26 mV at room temperature, electronic charge

)

A	Fill in the Blank Type Question

Discuss GATE EC 2016 Set 3 Electronic Devices and Circuits Basics of Semiconductors

Question 44 Explanation:

Question 45

Figures I and II show two MOS capacitors of unit area. The capacitor in Figure I has insulator materials X (of thickness t₁ = 1 nm and dielectric constant ε₁ = 4) and Y (of thickness t₂ = 3 nm and dielectric constant ε₂ = 20). The capacitor in Figure II has only insulator material X of thickness t_Eq. If the capacitors are of equal capacitance, then the value of t_Eq (in nm) is ______

A	Fill in the Blank Type Question

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Question 45 Explanation:

Question 46

The I-V characteristics of the zener diodes D1 and D2 are shown in Figure I. These diodes are used in the circuit given in Figure II. If the supply voltage is varied from 0 to 100 V, then breakdown occurs in

A	D1 only
B	D2 only
C	Both D1and D2
D	None of D1 and D2

Discuss GATE EC 2016 Set 3 Electronic Devices and Circuits Diodes and Its Applications

Question 46 Explanation:

Question 47

Which one of the following process is preferred to form the gate dielectric (SiO₂) of MOSFETs?

A	Sputtering
B	Molecular beam epitaxy
C	Wet oxidation
D	Dry oxidation

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 47 Explanation:

->Dry oxidation has a lower growth rate than wet oxidation although the oxide film quality is better than the wet oxide film. Therefore thin oxides such as screen oxide, pad oxide, and especially gate oxide normally use the dry oxidation process. Dry oxidation also results in a higher density oxide than that achieved by wet oxide and so it has a higher breakdown voltage (5 to 10 MV/cm)
->Dry oxidation is better than wet oxidation, so dry oxidation is always preferred for gate dielectric because we want precision.
Hence, the correct option is (D).

Question 48

If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TURE?

A	Current gain will increase
B	Unity gain frequency will increase
C	Emitter-base junction capacitance will increase
D	Early voltage will increase

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 48 Explanation:

As the base width is increased, the base current will increase thus reducing the collector current. The collector– emitter characteristics will be more flat, thus the extrapolation of collector currents will be farther i.e. Early voltage will increase.

Question 49

In the circuit shown in the figure, the BJT has a current gain (β) of 50. For an emitter-base voltage V_EB = 600 mV, the emitter-collector voltage V_EC (in Volts) is _____.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 49 Explanation:

Question 50

In the circuit shown, assume that diodes D₁ and D₂ are ideal. In the steady state condition, the average voltage V_ab (in Volts) across the 0.5 μF capacitor is _______.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 50 Explanation:

For positive half cycle, diode D₂ will be ON. So, peak voltage at point a is
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For negative half cycle, diode D1 will be ON. So, peak voltage at point b is

Hence V_ab= V_a− V_b
= 50 −(−50) 50+50= 100 V
At steady state, voltage across capacitor remains same i.e. 100V.
So average value=100V

Another Approach

Question 51

The electric field profile in the depletion region of a p-n junction in equilibrium is shown in the figure. Which one of the following statements is NOT TRUE?

A	The left side of the junction in n-type and the right side is p-type
B	Both the n-type and p-type depletion regions are non-uniformly doped
C	The potential difference across the depletion region is 700 mV
D	If the p-type region has a doping concentration of 10¹⁵ cm^–3, then the doping concentration in the n-type region will be 10¹⁶ cm^–3.

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Diodes and Its Applications

Question 51 Explanation:

In option (C) it is given as 700 mV, so it is not true.

Question 52

The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. When the drain-source voltage was increased to 6V while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to source saturation voltage is much smaller than the applied drain-source voltage. The channel length modulation parameter λ (in V^–1) is ____.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Basics of Semiconductors

Question 52 Explanation:

Question 53

In the circuit shown, both the enhancement mode NMO transistors have the following characteristics: k_n = m_n C_ox (W/L) = 1 mA/V²; V_TN= 1V. Assume that the channel length modulation parameter l is zero and body is shorted to source. The minimum supply voltage V_DD (in volts) needed to ensure that transistor M₁ operates in saturation mode of operation is _________

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Basics of Semiconductors

Question 53 Explanation:

Question 54

Two sequences x₁ [n] and x₂ [n] have the same energy. Suppose x₁[n] = a 0.5ⁿ u[n], where a is a positive real number and u[n] is the unit step sequence. Assume

Then the value of a is__________.

A	Fill in the Blank Type Question

Discuss GATE EC 2015 Set 3 Electronic Devices and Circuits Basics of Semiconductors

Question 54 Explanation:

x₁[n]= -(0.5)ⁿu[n]
Energy of signal x₁[n] is

Again, x₂[n] =

So, energy of signal x₂[n] is

Given that
Energy of signal x₁[n] = Energy of signal x₂ [n]

Since

is a positive real number, so we have
α = 1.5

Question 55

A piece of silicon is doped uniformly with phosphorous with a doping concentration 10¹⁶ /cm³. The expected value of mobility versus doping concentration for silicon assuming full dopant ionization is shown below. The charge of an electron is

C.
The conductivity (in S cm^–1) of the silicon sample at 300 K is____
Hole and Electron Mobility in Silicon at 300 K

A	1.82
B	1.92
C	192
D	150.2

Discuss GATE EC 2015 Set 2 Electronic Devices and Circuits Carrier Transport

Question 55 Explanation:

Question 56

An n-type silicon sample is uniformly illuminated with light which generates 10²⁰ electron hole pairs per cm³ second. The minority carrier lifetime in the sample is 1 μs. In the steady state, the hole concentration in the sample is approximately 10^x, where x is an integer. The value of x is___

A	4
B	14
C	2
D	12

Discuss GATE EC 2015 Set 2 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 56 Explanation:

->Rate of generation =10²⁰ electron-hole pairs per cm³ per second.
->At steady state (at the end of lifetime) t = 1μsec, concentration of hole-electron pair in 1 μsec is
= 10²⁰ ×10^–6 = 10¹⁴
So, x = 14

Question 57

A dc voltage of 10 V is applied across an n-type silicon bar having a rectangular cross-section and a length of 1 cm as shown in figure. The donor doping concentration N_D and the mobility of electrons

are 10¹⁶ cm^-3 and 1000 cm²V^–1s^–1, respectively. The average time (in μs) taken by the electrons to move from one end of the bar to other end is__________

A	100
B	200
C	300
D	400

Discuss GATE EC 2015 Set 2 Electronic Devices and Circuits Carrier Transport

Question 57 Explanation:

Given,

= 10⁴ cm/s

Question 58

When the optical power incident on a photodiode is 10μW and the responsivity is 0.8A/W, the photocurrent generated (inμA) is ________.

A	2
B	4
C	6
D	8

Discuss GATE EC 2014 Set 1 Electronic Devices and Circuits Basics of Semiconductors

Question 58 Explanation:

Question 59

The doping concentrations on the p-side and n-side of a silicon diode are
1 X 10¹⁶ CM^-3 and 1 X 10 ¹⁷ CM ^-3 , respectively. A forward bias of 0.3 V is applied to the diode. At T = 300K, the intrinsic carrier concentration of silicon The electron concentration at the edge of the depletion region on the p-side is

A
B
C
D

Discuss GATE EC 2014 Set 1 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 59 Explanation:

Question 60

A silicon bar is doped with donor impurities N_D = 2.25 x 10¹⁵ atoms / cm³. Given the intrinsic carrier concentration of silicon at T = 300 K is n_i = 1.5 x 10¹⁰ cm^-3. Assuming complete impurity ionization, the equilibrium electron and hole concentrations are

A
B
C
D

Discuss GATE EC 2014 Set 2 Electronic Devices and Circuits Basics of Semiconductors

Question 60 Explanation:

Question 61

Assume electronic charge

and electron mobility

If the concentration gradient of electrons injected into a P-type silicon sample is

the magnitude of electron diffusion current density (in A/cm2) is _________.

A
B
C
D

Discuss GATE EC 2014 Set 2 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 61 Explanation:

Question 62

Consider an abrupt PN junction (at T = 300 K) shown in the figure. The depletion region width X_n on the N-side of the junction is 0.2 μm and the permittivity of silicon (ε_si) is 1.044x10^-12 F/cm At the junction, the approximate value of the peak electric field (in kV/cm) is _________.

A	25.40
B	28.32
C	30.66
D	32.42

Discuss GATE EC 2014 Set 2 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 62 Explanation:

Question 63

When a silicon diode having a doping concentration of

on p-side and

on n-side is reverse biased, the total depletion width is found to be 3μm. Given that the permittivity of silicon is

the depletion width on the p-side and the maximum electric field in the depletion region, respectively, are

A
B
C
D

Discuss GATE EC 2014 Set 2 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 63 Explanation:

Question 64

A thin P-type silicon sample is uniformly illuminated with light which generates excess carriers. The recombination rate is directly proportional to

A	The minority carrier mobility
B	The minority carrier recombination lifetime
C	The majority carrier concentration
D	The excess minority carrier concentration

Discuss GATE EC 2014 Set 3 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 64 Explanation:

Recombination rate, R = B(n_{n_o} + n_n) (P_{n_o} + P_n)
n_{n_o} and P_{n_o} = Electron and hole concentrations respectively under thermal equilibrium
n_n and p_n =Excess elements and hole concentrations respectively

Question 65

The donor and accepter impurities in an abrupt junction silicon diode are
1 x 10¹⁶ cm^-3 and 5 x 10¹⁸ cm^-3, respectively. Assume that the intrinsic carrier concentration in silicon n_i = 1.5 x10¹⁰ cm^-3 at 300K, kT/q =26 mV and the permittivity of silicon

The built-in potential and the depletion width of the diode under thermal equilibrium conditions, respectively, are

A	0.7 V and 1 x 10^-4 cm
B	0.86 V and 1 x 10^-4 cm
C	0.7 V and 3.3 x 10^-5 cm
D	0.86 V and 3.3 x 10^-5 cm

Discuss GATE EC 2014 Set 3 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 65 Explanation:

Question 66

At T = 300 K, the band gap and the intrinsic carrier concentration of GaAs are 1.42 eV and 10⁶ cm^-3 respectively. In order to generate electron hole pairs in GaAs, which one of the wavelength

ranges of incident radiation, is most suitable? (Given that: Plank’s constant is

velocity of light is

and charge of electron is

A
B
C
D

Discuss GATE EC 2014 Set 4 Electronic Devices and Circuits Energy Bands and Generation Of Carriers

Question 66 Explanation:

Energy of each photon in radiation is given by,

Now, since energy required is more than band gap and energy is inversely proportional to wavelength.
Therefore, λ<0.87μm

Question 67

In the figure in

is plotted as a function of 1/T, where

the intrinsic resistivity of silicon, T is is the temperature, and the plot is almost linear.

The slope of the line can be used to estimate

A	Band gap energy of silicon (Eg)
B	Sum of electron and hole mobility in silicon
C	Reciprocal of the sum of electron and hole mobility in silicon
D	Intrinsic carrier concentration of silicon

Discuss GATE EC 2014 Set 4 Electronic Devices and Circuits Basics of Semiconductors

Question 67 Explanation:

Question 68

The cut-off wavelength (in μm) of light that can be used for intrinsic excitation of a semiconductor material of bandgap Eg= 1.1 eV is ________

A	0.85 μm
B	1.125 μm
C	1.450 μm
D	2.250 μm

Discuss GATE EC 2014 Set 4 Electronic Devices and Circuits Basics of Semiconductors

Question 68 Explanation:

Question 69

Consider a silicon sample doped with N_D = 1×10¹⁵ /cm³donor atoms. Assume that the intrinsic carrier concentration n_i = 1.5×10¹⁰ /cm³_.If the sample is additionally doped with N_A = 10×10¹⁸ /cm³ acceptor atoms, the approximate number of electrons/cm³ in the sample, at T=300 K, will be _________________.

A	22.52
B	245.2
C	255.2
D	265.2

Discuss GATE EC 2014 Set 4 Electronic Devices and Circuits Basics of Semiconductors

Question 69 Explanation:

Question 70

An N-type semiconductor having uniform doping is biased as shown in the figure.

is the lowest energy level of the conduction band,

is the highest energy level of the valance band and

is the Fermi level, which one of the following represents the energy band diagram for the biased N-type semiconductor?

A
B
C
D

Discuss GATE EC 2014 Set 4 Electronic Devices and Circuits Basics of Semiconductors

Question 70 Explanation:

In N-type, Semiconductor E_f lies near to the conduction Band and since it is positively biased on right side so energy band diagram will be tilted downwards on right side, hence option D is the correct answer.

Question 71

In a forward biased pn junction diode, the sequence of events that best describes the mechanism of current flow is

A	injection, and subsequent diffusion and recombination of minority carriers
B	injection, and subsequent drift and generation of minority carriers
C	extraction, and subsequent diffusion and generation of minority carriers
D	extraction, and subsequent drift and recombination of minority carriers

Discuss GATE ECE 2013 Electronic Devices and Circuits Diodes and Its Applications

Question 71 Explanation:

Potential barrier of the pn junction is lowered when a forward bias voltage is applied, allowing electrons and holes to flow across the space charge region (Injection) when holes flow from the p region across the space charge region into the n region, they become excess minority carrier holes and are subject to diffuse, drift and recombination processes.
(i) holes will be injected from p-side.
(ii) holes will be diffused in n-side.
(iii)Recombination will take place.

Question 72

In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces

A	superior quality oxide with a higher growth rate
B	inferior quality oxide with a higher growth rate
C	inferior quality oxide with a lower growth rate
D	superior quality oxide with a lower growth rate

Discuss GATE ECE 2013 Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 72 Explanation:

In IC technology, The electrical properties of dry oxidation is better than wet oxidation. But it is a low processor
Dry oxidation as compared to wet oxidation produces superior quality oxide with a lower growth rate

Question 73

The i–v characteristics of the diode in the circuit given below are

The current in the circuit is

A	10 mA
B	9.3 mA
C	6.67 mA
D	6.2 mA

Discuss GATE ECE 2012 Electronic Devices and Circuits Diodes and Its Applications

Question 73 Explanation:

Let v > 0.7 V and diode is forward biased. By applying Kirchoff’s voltage law
10- (1000) i – v = 0 ...(1)
since 10 V is greater than 0.7 v so current will flow through diode and is
from (1) and (2) we have

Question 74

The source of a silicon (n_i = 10¹⁰ per cm³) n-channel MOS transistor has an area of 1 sq pm and a depth of 1 pm. If the dopant density in the source is 10¹⁹/cm³, the number of holes in the source region with the above volume is approximately

A	10⁷
B	100
C	10
D	0

Discuss GATE ECE 2012 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 74 Explanation:

n_i = 10¹⁰ / cm³
A = 1 × 10^-12 m²
d = 10^-6 m
V = Ad = 10^-18 m³
= 10^-12 cm³
N_D = n = 10¹⁹ / cm³

= 10 / cm³
So holes in volume V is
H = pV = 10^-11
Since holes number cannot be a decimal number so H = 0.

Question 75

In the three dimensional view of a silicon n-channel MOS transistor shown below. δ = 20 mn. The transistor is of width 1 µm. The depletion width formed at every p-n junction is 10 mn. The relative permittivities of Si and SiO₂, respectively, are 11.7 and 3.9. and ε₀ = 8.9 x 10^–12 F/m.

The gate-source overlap capacitance is approximately

A	0.7 fF
B	0.7 pF
C	0.35 fF
D	0.24 pF

Discuss GATE ECE 2012 Electronic Devices and Circuits Basics of Transistors and MOSFETs

Question 75 Explanation:

Gate source capacitance C_g is

∈_r1 = 3.9 as between gate and source there is SiO₂
A₁ = 1μm × δ = 1 × 10^-6 × 20 × 10^-9
= 2 × 10^-14 m²
d₁ = 1nm = 10^-9 m
So,

C_g = 69.42 × 10^-17 F
C_g = 0.69 × 10^-15
C_g = 0.7fF

Question 76

Which of the following are the advantages of Silicon over Insulator (SOI)?
1) Lower diffusion capacitance
2) Smaller parasitic delay and lower dynamic power consumption
3) Lower threshoid voltages
Select the correct answer using the code given below.

A	1, 2 and 3
B	1 and 2 only
C	1 and 3 only
D	2 and 3 only

Discuss ESE 2019 Paper 2(Technical) Electronic Devices and Circuits Diodes and Its Applications

Question 76 Explanation:

Advantages of Silicon Over Insulator
1. Lower diffusion capacitance
2. Lower parasitic delay
3. Lower threshold voltage.
4. Lower dynamic power consumption.

Question 77

In EPROMs, applying a high voltage to the upper gate causes electrons to jump through the thin oxide onto the floating gate through the process known as

A	mask programming
B	one-time programming
C	avalanche injection or Fowler-Nordheim tunneling
D	erasing

Discuss ESE 2019 Paper 2(Technical) Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 77 Explanation:

In EPROM, applying a high voltage to the upper gate causes electrons to jump through the thin oxide into the floating gate through the process known as a valance injection or Fowler–Nordeim tunneling .
Applying a ‘high voltage’ to the control gate causes ‘Avalanche Injection’ in the EPROMS. Due to this electrons overcome the resistance offered by SiO₂ layer and gets trapped on the floating gate.

Question 78

The following six (6) items consist of two statements, one labelled as ‘Statement (I)’ and the other as ‘Statement (II)‘. You are to examine these two statements carefully and select the answers to these items using the code given below:
Statement (I): The external surface of a crystal is an imperfection in itself as the atomic bonds do not extend beyond the surface.
Statement (II): The external surfaces have surface energies that are related to the number of bonds broken at the surface.

A	Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)
B	Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)
C	Statement (I) is true but Statement (II) is false
D	Statement (I) is false but Statement (II) is true

Discuss ESE 2019 Paper 2(Technical) Electronic Devices and Circuits Crystalline Structures

Question 78 Explanation:

Question 79

The following six (6) items consist of two statements, one labelled as ‘Statement (I)’ and the other as ‘Statement (II)‘. You are to examine these two statements carefully and select the answers to these items using the code given below:
Statement (I): By organizing various ‘optical functions into an ‘array structure’ via nano-pattern replication, ‘spatial integration’ is established.
Statement (II): By adding a nano-optic layer or layers to functional optical materials, the ‘hybrid integration’ is possible to be achieved!

A	Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)
B	Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)
C	Statement (I) is true but Statement (II) is false
D	Statement (I) is false but Statement (II) is true

Discuss ESE 2019 Paper 2(Technical) Electronic Devices and Circuits integrated Circuit Fabrication Process

Question 79 Explanation:

Statement (I) and Statement (II) are correct and Statement (II) is not correct explanation of Statement (I).

Nano-optic elements consists of numerous nano scale structure created by replicating nano pattern masters, with spatial integration method is established.
In hybrid integration method, discreate nono-optic devices are produced by adding a nano-optic layer or layers.
Hybrid integration can be achieved by adding a nano-optic layer or layers to functional optical materials. The process by which nano-optic elements are fabricated is flexible and robust, allowing for cost-saving manufacturing process integration in creating hybrid optics.

Question 80

Which of the following semiconductor compund is not used in the construction of Light Emitting Diodes?

A	GaAs
B	GaP
C	GaSe
D	GaN

Discuss ISRO EC 2018 Electronic Devices and Circuits Basic Electronics Engineering

Question 80 Explanation:

The Correct Answer Among All the Options is C
GaSe compound does not exist .
Refer the Topic Wise Question for Basic Electronics Engineering Electronic Devices and Circuits

Question 81

An ideal p-n junction diode in seris with a 100

resistance is forward biased such that the forward current flowing through the diode is 100 mA. If voltage across this circuit is instantaneously reversed to 20 V at time instant t = to, then the reverse current flowing through the diode at time instant t = to is approximately given by

A	0 mA
B	200 mA
C	100 mA
D	2 mA

Discuss ISRO EC 2018 Electronic Devices and Circuits Basics of Semiconductors

Question 81 Explanation:

The Correct Answer Among All the Options is B
if a diode is conducting in forward bias and immediately switched to reverse bias voltage , the diode will allow to flow the current in reverse bias for short time so that the forward voltage bleeds off, (or we can say for the time which diode takes to be in complete reverse bias, it act as a short circuit). This is called reverse recovery time.

I =

= 200mA.
Refer the Topic Wise Question for Basics of Semiconductors Electronic Devices and Circuits

Question 82

Electric Field of 1 V/m is applied to a Boron doped Silicon semiconductor slab having doping density of 10¹⁶ atoms/cm³ at 300K temperature. Determine the approcimate resistivity of the slab. (Consider intrinsic carrier concentration of Silicon at 300 K = 1.5 x 10¹⁰ / cm³ Hole Mobility =500 cm²/Vs at 300 K; Electron Mobilty = 1300 cm²/Vs at 300 K).

A	0.48 -cm
B	0.35 -cm
C	0.16 -cm
D	1.25 -cm

Discuss ISRO EC 2018 Electronic Devices and Circuits Carrier Transport

Question 82 Explanation:

The Correct Answer Among All the Options is D
conductivity of extrinsic semiconductor(

)= nq

+pq

here , n and p are no. of electrons and protons respectively
q=1.6

=1300 cm²/Vs

500 cm²/Vs
As it is Boron doped Silicon semiconductor so it is p-type.
Therefore p=

=10¹⁶ atoms/cm³
Using mass action law , n=

Then ,

= 1.6

)
,

Resistivity (

) =

=1.25

-cm
Refer the Topic Wise Question for Carrier Transport Electronic Devices and Circuits

Question 83

In metals, the thermal conductivity K and electrical conductivity 6 are related as

L is known as

A	Lattice constant
B	Lorenz number
C	Lanevin Function
D	Larmor number

Discuss ISRO EC Dec 2017 Electronic Devices and Circuits Conductive Materials and Superconductors

Question 83 Explanation:

The Correct Answer Among All the Options is B
Here, L=Lorenz number
Lorenz number is widely used for the determination of k_E in case of σ measurements. The given equation is called as Widemann-Franz law and it states that the ratio of the contribution(electrical) done by the thermal conductivity(k) to conductivity(σ) in a certain metal is directly proportional to the temperature 'T'.
L=2.44 x 10^-8wΩk^-2
Refer the Topic Wise Question for Conductive Materials and Superconductors Electronic Devices and Circuits

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