Digital Logic Design | Subject Wise

Maximum Binary Numbers Possible using n-bit   =  2ⁿ -1
Maximum Ternary  Numbers Possible using x-bit in = 3^x -1
Ternary and Binary take different Number of bits to represent same number.
i.e, Maximum value representable in ternary system using x digits = Maximum value representable in binary system using  n digits
3^x -1 =  2ⁿ -1
3^x =  2ⁿ
Now, taking log on both side :
X= log₃ ( 2ⁿ  )
X=n*log₃2

• Output of AND gate 1 will be available at the input of OR gate after (Inverter Time and AND gate1 Time) = 9+10 = 19ns
• It means AND gate 1 will take = 9+10 = 19ns
• Output of AND gate 2 will be available at the input of OR gate after(only AND gate2 Time) = 12 ns
• A Glitch will be generated for (AND gate1 Time)-(AND gate2 Time) = 19-12 = 7ns

• NOR and NAND are the universal gates
• Any logic gate can be implemented by using these NOR and NAND logic gates.
• NOR and NAND are Functionally Complete

Option(A) : {AND, OR}
These two gates do not make a universal gate they are just Basic gates.

Option(B) : {AND, NOT} = NAND = Functionally Complete
Combining these two gates we can make NAND gate which is again a universal gate.

Option(C) : {NOT, OR}} = NOR = Functionally Complete
Combining these two gates we can make NOR gate which is again a universal gate.

Option(D) : NOR = Functionally Complete
NOR is a universal gate.

So we can conclude that Option(A) is Correct Answer

Suppose a number 128 is to represented as a bit-field then its width would be [log₂(n)] + 1
Therefore, ((log₂ 128) + 1) = 7 + 1 = 8 bits are required to represent 128
Note : A number of the form 2^x has x+1 bits.
Thus any number chosen in between (0,n] should have [log₂ (n)]+1 bits.

Given
√(224)_r = (13)_r
Squaring both sides
(√(224)_r)²= ((13)_r)²

Above  equation can be written as: (224)_r = ((13)_r)²
Converting to decimal number:  
2r² + 2r¹ + 4r⁰ = (1r¹ + 3r⁰)²
2r² + 2r + 4 = (r + 3)²
r² - 4r - 5 = 0
r² - 5r  + r - 5 = 0
⟹(r−5)(r+1)=0

Root of the above equation is 5, -1.
r being a base, it can not be −1.

Therefore radix = 5

• radix r =10,  13 is not the root of 224
• radix r =8,  224_r = (64*2+8*2+4) =128+20 =148  (not a perfect square)
• radix r =6,  224_r = (36*2+6*2+4) =72+16 =88 ( not a perfect square)
•  radix r =5, 224_r = (25*2+5*2+4) =50+14 =64 (perfect square) i.e,√64 =8 =(13)₅

y=(a+b'+a'b)c'
y=[a+(b'+a')(b'+b)]c' ∴ distributive law
y=[a+(b'+a').1]c'  ∴ b'+b=1
y=(a+b'+a')c'
y=(a+a'+b')c'
y=(1+b')c'          ∴a+a'=1
y=c'                   ∴1+b'=1

Implement Full Subtractor using 2 half Subtractors and one OR gate :

• Full Subtractor using 2 half Subtractors and one OR gate as follow:
• The foremost disadvantage of the half subtractor is, we cannot make a Borrow bit in this subtractor. Whereas in its design, actually we can make a Borrow bit in the circuit and can subtract with the remaining two i/ps.
• Here A is minuend, B is subtrahend & Bin is borrow in. The outputs are Difference (Diff) & Bout (Borrow out). The complete subtractor circuit can obtain by using two half subtractors with an extra OR gate.

Implement Full Subtractor using 2 half Subtractors and one OR gate as follow :


Below circuit can be done with two half-Subtractor circuits. In the initial half-Subtractor circuit, the binary inputs are A and B. It will generate two outputs namely difference (Diff) & Borrow.

• The difference o/p of the left subtractor is given to the Left half-Subtractor circuit’s. Diff output is further provided to the input of the right half Subtractor circuit. We offered the Borrow in bit across the other i/p of the next half subtractor circuit. Once more it will give Diff out as well as Borrow out the bit. The final output of this subtractor is Diff-output.
• On the other hand, the Borrow out of both the half Subtractor circuits is connected to OR logic gate. Later than giving out OR logic for two output bits of the subtractor, we acquire the final Borrow out of the subtractor. The last Borrow out to signify the MSB (a most significant bit).

 

In Excess-3 code

• If a carry is there = Add 3 with the result
• No carry = Subtract 3 from the result
• For 9  it does not produce the carry, Hence 0011(3) will be subtracted from sum to get actual value of BCD.

1. SR Flip flop: Q_next = S+R'Q
2. JK Flip flop: Q_next =JQ'+ K'Q
3. D Flip flop Q_next = D
4. T Flip flop Q_next = T ⊕  Q

The optical encoder is a transducer commonly used for measuring rotational motion. It consists of a shaft connected to a circular disc, containing one or more tracks of alternating transparent and opaque areas.

An optical encoder has several tracks, with different patterns on each, to produce a binary code output that is unique for each encoded position. There is a track for each output bit, so an 8-bit absolute encoder has 8 tracks, 8 outputs and 256 output combinations, for a resolution of 360/256 = 1.4°.

3 x 512 + 7 x 64 + 5 x 8 + 3

= (2 + 1) x 2⁹ + (4 + 2 + 1)2⁶ + (4 + 1)2³ + (2 + 1)

= 2¹⁰ + 2⁹ + 2⁸ + 2⁷ + 2⁶ + 2⁵ + 2³ + 2¹ + 1

= 2¹⁰ + 2⁹ + 2⁸ + 2⁷ + 2⁶ + 2⁵ + 2³ + 2¹ + 2⁰

=11111101011

Note : 2¹⁰ (10 0's followed by 1) , 2⁹ (9 0's followed by 1) ..  ..  ..  ....  ..

Therefore Total Number of 1's =9

(0.75)₁₀ = (0.110)₂ = (0.60)₈
The Octal equivalent of (0.75)₁₀= (0.60)₈

Option(c) is Correct ANSWER

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0 lead to a forbidden state
forbidden state Means  State is invalid state and must not be entered and Not sure of the output and Output changes continuously
This is different from an indeterminate state which means a state where we are not sure of the output.
This is different from an a toggling state where the output changes continuously.

Source : Morris Mano
When both R and S are set as 0, we will get both Q and Q’ as 1. This output will be permanent and it is not dependent on any order of occurrence it only depends on the input values [NO RACE CONDITION].

But after this state if we make R=S=1, the output will be indeterminate depending on which NAND gate processes first (either Q or Q’ will become 0 but we can’t determine which [RACE CONDITION] and it will lead to an indeterminate state.

A ring counter is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.  for each clock pulse, counter advances switch by one step like in sequential gating systems. So, it works similar as a Stepping Switch.

There are two types of ring counters:

• A straight ring counter, also known as a one-hot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
• A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.

Reference : https://en.wikipedia.org/wiki/Ring_counter

TL gates operate on a nominal power supply voltage of 5 volts, +/- 0.25 volts. Ideally, a TTL “high” signal would be 5.00 volts exactly, and a TTL “low” signal 0.00 volts exactly.

However, real TTL gate circuits cannot output such perfect voltage levels, and are designed to accept “high” and “low” signals deviating substantially from these ideal values.

“Acceptable” input signal voltages range from 0 volts to 0.8 volts for a “low” logic state, and 2 volts to 5 volts for a “high” logic state.

“Acceptable” output signal voltages (voltage levels guaranteed by the gate manufacturer over a specified range of load conditions) range from 0 volts to 0.5 volts for a “low” logic state, and 2.7 volts to 5 volts for a “high” logic state:

Representation of Floating point number will be = -1^S x M x 2^E
Given
Mantissa = 16 bit
Exponent = 8 bit

LARGEST NUMBER
LARGEST NUMBER means it should be largest positive number it consists of both largest positive Mantissa and Exponent

• Given mantissa is 16-bit so largest positive mantissa value possible is 0111 1111 1111 1111 (+2¹⁵-1 in 2's complement)
• Given exponent is 8-bit so largest positive exponent value possible is 0111 1111 (+2⁷-1 (+127) in 2's complement)

Finally largest positive number is (+2¹⁵-1) x 2¹²⁷

SMALLEST NUMBER

• Given mantissa is 16-bit so Smallest mantissa value is 0000 0000 0000 0000( 1 is present always at rightmost always 1) = 1
• Given exponent is 8-bit so Largest negative exponent value is (smallest exponent value is) 1111 1111 (-2⁷ (-128) in 2's complement)

Finally smallest positive number is (1 x 2^-128)

Note : Exponents are given as power of 10. in the options it should be 2

BASIS FOR COMPARISON	SRAM	DRAM
Speed	Faster	Slower
Size	Small	Large
Cost	Expensive	Cheap
Used in	Cache memory	Main memory
Density	Less dense	Highly dense
Construction	Complex and uses transistors and latches.	Simple and uses capacitors and very few transistors.
Single block of memory requires	6 transistors	Only one transistor.
Charge leakage property	Not present	Present hence require power refresh circuitry
Power consumption	Low	High

Given Binary Number = 01111100110111100011
Split into 4 term each then we get a Hexadecimal

• In order to Represent 256 in Binary we require 8 bits  i.e, log₂ (256) = 8 bits.
• Similarly in Ternary representation, we require 5 bits i.e, log₃ (256) ≈ 5.047 bits
• Now rounding off to the upper integer (since number of bits is an integer) and we get 6
• So Answer should be 6 Flits(Bits)(256=100111₃)

We need 32K×32 bit RAM
We have RAM chips capacity 128×8 bit
Number of RAMs required = (32 * K * 32) / 128 * 8
Number of RAMs required = (2⁵ * 2¹⁰ * 2⁵ ) / ( 2⁷ * 2³)  ∴ k=2¹⁰
Number of RAMs required = 2²⁰ / 2¹⁰
Number of RAMs required = 1024

NAND and NOR gates are universal gates. By using of these gates we can realize any gate.

Minimum 3 NAND gates are required to implement an OR gate = A+B = ((A + B)')' = ( A' .B' )'

When two n-bit binary numbers are added the sum will contain at the most (n+1) bits

Example : add 2 decimal numbers let say 3 + 3 equivalent binary representation will be (11)₂ +(11)₂

Given number is in base 8 thus each digit can be represented in three binary bits to get overall binary equivalent.
1 => 001
2 => 010
1 => 001
7 => 111
so 16 digit binary equivalent of 1217 is
001 010 001 111
now group it to four digit number
0010 1000 1111
which is (2 8 F)₁₆

(1217)₈ = (001 010 001 111)₈ = (0010 1000 1111) = (28F)₁₆

None of the above

N² = (7601)₈
N² = 7 * 8³ + 6*8²+ 0*8¹ + 1*8⁰
N² = 7*8*8*8 + 6*8*8 + 0 + 1*8
N² = 3969
N = (63)₁₀

Now consider the option

(241)₅ = 2*5*5 + 4*5 + 1 = 71
Option (A) is incorrect.

(143)₆ = 1*6*6 + 4*6 + 3 = 63
Option (B) is correct.

(165)₇ =  1*7*7 + 6*7 +5 = 95
Option (C) is incorrect.

we know that Radix > digit

• From LHS : (12x)₃ tells us that the value of x should be less than 3
• From RHS : (123)_x tells us that the value of x should be greater than 3 because  largest digit among 123 is 3.

Given that
Computer uses 8 digit mantissa and 2 digit exponent :

In standard form : a = 0.052 = 0.52 E-1;  mantissa = 0.52,exponent = −1.
it means a=0.052 can be represented in M*E by a = 0.052 = 0.52 * 10^-1

In standard form : b = 28E+11 =0.28 E+13; mantissa = 0.28, exponent = 13.
it means b= 28E+11 can be represented in M*E by b = 28E+11 = 0.28*10¹³

To add b+a, Small exponent number (a) is shifted to (13-(-1) =14) Therefor 14 places to right side
a = 0.0000000000000052E+13.

But, computer uses only 8 digit mantissa,
digits beyond 8th position will be discarded.

So a = 0.00000000E+13 = 0.0 E+13
b + a = (0.28E + 13) + (0.0E + 13 ) = 0.28E + 13
Then b + a - b = (0.28E + 13) - (0.28E + 13) = 0

Given Boolean expression ( A + C’)(B’+ C’)
(A+C')(B'+C')
AB'+AC'+BC'+C'
AB'+(A+B+1)C'  //taking C' common
AB'+(1)C' // A+1=1
We Know ( 1*C' =C')
So required expression AB'+C' .

A'(A’ + B’)
= A'A' + A'B'
= A' + A'B' // A*A=A
= A'(1 + B') // Taking A' as common
= A'(1) // 1 + B' = 1
= A' // A*1=A

Figure : 1 = x'y'
Figure : 2 = xy'
Entirely different

IN EX-OR output is 1 When inputs are different otherwise 0

• 0 XOR 0 =0
• 0 XOR 1 =1
• 1 XOR 0 =1
• 1 XOR 1 =0  

In the above function implemented with Ex-OR Gate and both the inputs of the first Ex-OR gate are set to 0. Then the output is also 0 the further two gates are also getting 0 as both their inputs

The function continue to generate 0

IN EX-OR output is 1 When inputs are different otherwise 0

TRUTH TABLE

• 0 XOR 0 =0
• 0 XOR 1 =1
• 1 XOR 0 =1
• 1 XOR 1 =0  

 

• The gray code which is also known as the reflected binary code is a binary numeral system where two successive values differ in only one bit position at a time.
• Gray codes are less error-prone for mechanical devices that involve making and breaking electrical circuits because they only change in one bit position at a time.
• Gray code  considered as the minimum error code.

Roundoff error is the difference between an approximation of a number used in computation and its exact (correct) value. In certain types of computation, roundoff error can be magnified as any initial errors are carried through one or more intermediate steps and repeated execution.

To construct 2¹⁰ x 1-MUX using 2x1 MUX:

1024/2 = 512
512/2=256
256/2=128
128/2=64
64/2=32
32/2=16
16/2=8
8/2=4
4/2=2
2/2=1

Now add all the values  512+256+128+64+32+16+8+4+2+1=1023 MUX

Outcome from the question : In general, The number of N-input Multiplexers needed to create a M-input multiplexer (M > N) is,

For n bit 2’s complement numbers, range of number is -(2^(n-1)) to +(2^(n-1)-1)

• Number of distinct numbers that can be represented using n bits = 2ⁿ
• In Unsigned numbers these corresponds to numbers from 0 to 2ⁿ−1.
• In Signed numbers in 1′s complement or sign magnitude representation, these corresponds to numbers from −(2ⁿ⁻¹−1) to ( 2ⁿ⁻¹ −1 )   with 2 separate representations for 0.)
• In Signed numbers in 2′s complement representation, these corresponds to numbers from (−2ⁿ⁻¹ ) to (2ⁿ⁻¹ −1 )   with a single representation for 0.

Both numbers are given in 2’s complement form.

01001101
+11101001
—————
100110110

Carry flag =1,
Overflow flag = 0,
Sign bit = 0

Note :
In 2′s complement addition Overflow happens only when:

• Sign bit of two input numbers is 0, and the result has sign bit 1
• Sign bit of two input numbers is 1, and the result has sign bit 0.

When two unsigned numbers are added, overflow occurs if

• there is a carry out of the leftmost bit.

Both numbers are given in 2’s complement form.
1101 (-3)
0100 (4)
-------
0001 (1)

It is -3+4=1, so no overflow
carry bit =1

Note :
In 2′s complement addition Overflow happens only when:

• Sign bit of two input numbers is 0, and the result has sign bit 1
• Sign bit of two input numbers is 1, and the result has sign bit 0.

When two unsigned numbers are added, overflow occurs if

• there is a carry out of the leftmost bit.

f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12)
On solving above k-map we get BC’D’ + A’C’D + AB’D

F (w, x, y,z) = Σ(1, 3, 4, 6, 9, 11, 12, 14] On solving K-MAP we get ZX’+XZ’
therefore  it is independent of w,y
it means w,y are not required to represent above function f

A + AB' + AB'C
A + AB'(1 + C)
A + AB'
A(1 + B')
A

So no NAND gate required

A(B+C) + AB + (A+B)C
AB+AC+AB+AC+BC
AB+AC+BC

w' + w'z + z'xy
= w'(1 + z) + z'xy
= w' + z'xy
Gate number 2 which produces w'z is redundant as it has been eliminated in final result
So, option (B) is correct

• Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays. Hazards occur in combinational circuits, where they may cause a temporary false output value. When they occur in asynchronous sequential circuits hazards may result in a transition to a wrong stable state.
• When the output changes several times then it should change from 1 to 0 or 0 to 1 only once, it is called "dynamic hazard".
• Dynamic hazard occur when the output changes for two adjacent input combinations while changing, the output should change only once. But it may change three or more times in short intervals because of different delays in several paths. Dynamic hazards occur only in multilevel circuit.

X1 = Y1
X2= Y1⊕Y2
X3=X2⊕Y3=Y1⊕Y2⊕Y3
NONE OF THE MATCHING

If we give the input 0 then we get Output  1
And then it (1) feedbacks to circuit again as input which will generate 0.
So it keep on oscillating between 0-1-0-1-0-1-0-1-0-1.....
Given circuit is logically equivalent to square wave.
option(D) is not correct because input and output are not same .Delay should have been ok if output would have been same with input.

Step 1 : convert into Binary
Step 2 : Make 3 bits into single group from LSB to MSB
Step 3 : Append 0's in the last block as MSB's if sufficient bits are not there

Given (12A7C)₁₆
(12A7C)₁₆= (0001 0010 1010 0111 1100)₂
(12A7C)₁₆= (000 010 010 101 001 111 100)₂
(12A7C)₁₆= (0225174)₈

The excess-3 code (or XS3) is a non-weighted code used to express decimal numbers. It is a self-complementary binary coded decimal (BCD) code and numerical system which has biased representation

Excess-3 codes are unweighted and can be obtained by adding 3 to each decimal digit then it can be represented by using 4 bit binary number for each digit. An Excess-3 equivalent of a given binary binary number is obtained using the following steps:

• Find the decimal equivalent of the given binary number.
• Add +3 to each digit of decimal number.
• Convert the newly obtained decimal number back to binary number to get required excess-3 equivalent.

Given  (P + Q’ + R’) . (P + Q’ + R) . (P + Q + R’)
(P+Q'+R')=011=3
(P+Q'+R)=010=2
(P+Q+R')=001=1
π=(1,3,2) =∑ (0,4,5,6,7) From the above K-map, POS form is :
P + Q’.R’

• In 1’s complement  transforming the 0 bit to 1 and the 1 bit to 0.
• 2’s complement  add 1 to the 1’s complement of the binary number.

a) 1010

• 1's complement = 0101
• 2's complement = 0110

b) 0101

• 1's complement = 1010
• 2's complement = 1011

c) 1000

• 1's complement = 0111
• 2's complement =1000

d) 1001

• 1's complement = 0110
• 2's complement = 0111

Hence Option(c) 1000 is correct.

JK Flip Flop accepts both inputs 1,1 which is not accepted by SR Flip Flop (it gives invalid output)

(X⊕Y)⊕Y = (X⊕Y)'Y+(X⊕Y)Y'
(X⊕Y)⊕Y = (XY+X'Y')Y + (XY'+X'Y)Y'+ // (X⊕Y)'=X XNOR Y
(X⊕Y)⊕Y =XY'+X'YY'+XY+X'Y'Y
(X⊕Y)⊕Y =XY'+0+XY+0
(X⊕Y)⊕Y =XY'+XY
(X⊕Y)⊕Y=X

Simple Method : XOR is Associative
(X⊕Y)⊕Y=X⊕(Y⊕Y)
(X⊕Y)⊕Y=X⊕0
(X⊕Y)⊕Y=X

Given 32-bit, single precision floating point IEEE representation
Floating Point number in Hexadecimal = C1D00000

C1D00000 = ( 1100 0001 1101 0000 0000 0000 0000 0000 ) in Binary

• In 32-bit, single precision floating point IEEE representation,
• 1^st MSB represents Sign of mantissa : ( 0 = positive value of mantissa and 1 = negative value mantissa  )
• Next 8 bits are for Exponent value
• Last 23 bits represents Mantissa.

So , S =1bit , Exponent= 8 bits , Mantissa = 23 bits.
First bit = sign bit = 1, so number is negative

• Exponent value =131−127 = 4 (127 is the bias in IEEE representation).
• Mantissa = -1.101000000...0
• Floating point number = -1.10100...0000
• Now Convert to decimal  = (1)2⁰+(1)2⁻¹+(0)2⁻²+(1)2⁻³ =1+1/2+0+1/8=13/8

Hence we finally get( sign * 2^exponent * mantissa) = -26

(X+Y)(X+Z)
XX +XZ +YX +YZ
X+X+XY+YZ   //(X*X=X)
X+XY+YZ  //X+X=X
X(1+1.Y)  + YZ    // TAKING X AS COMMON
X(1+Y)  + YZ   // 1.Y =Y
X  + YZ   // 1+Y=1
(X+Y)(X+Z) =X+YZ

When the Set line is set high and the Reset line is set low, then the RS flipflop has the state set to 1.

Since 8 bits = 1 byte
Each RAM chip has 128 x 8 = 1024 bits
2048 Bytes = 2048 x 8 bits = 16384 bits
Method 1 :
Number of 128 x 8 chips  = Required Total Memory (16384)/1024 = 16
Method 2 :
Number of 128 x 8 chips = Required Total Memory (2048)/128 = 16

The Hamming Distance between the two codeword: XOR between 2 valid codeword will give another valid codeword, The number of 1's in the valid codeword will indicate hamming distance(d).

OxAA= (1010 1010)₂
Ox55 = (0101 0101)₂
-----------------------
XOR = (1111 1111)₂

Number of 1's in (1111 1111)=8
∴Hamming distance = 8
Note : All the bits of both the words are different with respect to each other, so, the Hamming Distance is equal 8.

(42.75)₁₀ = (?)₂

42 you can convert directly from decimal to binary
(42)₁₀ =( 101010 )₂

Now convert Fractional part into binary
Multiply Fractional part with 2 until  fractional part becomes zero
.75
.75 * 2 =1.5  // Fractional part is .5 != 0
.5 * 2 = 1.0  // Fractional part is .0 == 0 So now stop

Now append all this MSBs(for 1.5=1, 1.0=1) to Binary Number
 (42.75)₁₀ = (101010.11)₂

In case of BCD the binary number formed by four binary digits, will be the equivalent code for the given decimal digits. In BCD we can use the binary number from 0000-1001 only, which are the decimal equivalent from 0-9 respectively. Suppose if a number have single decimal digit then it’s equivalent Binary Coded Decimal will be the respective four binary digits of that decimal number and if the number contains two decimal digits then it’s equivalent BCD will be the respective eight binary of the given decimal number. Four for the first decimal digit and next four for the second decimal digit. It may be cleared from an example.

Let, (12)₁₀ be the decimal number whose equivalent Binary coded decimal will be 00010010. Four bits from L.S.B is binary equivalent of 2 and next four is the binary equivalent of 1.

Let us consider the base be x
(1102)₃ = (123)_x
(1102)₃=1⨉3³+1⨉3²+2=38
(123)_x=1⨉x²+2x+3
Therefore, 38 = 1⨉x²+2x+3
x=5

• NOR and NAND are the universal gates
• Any logic gate can be implemented by using these NOR and NAND logic gates.
• NOR and NAND are Functionally Complete

Option(C) : {AND, OR}
These two gates do not make a universal gate they are just Basic gates.

Option(D) : {AND, NOT} = NAND = Functionally Complete
Combining these two gates we can make NAND gate which is again a universal gate.

Option(A) : {NOT, OR}} = NOR = Functionally Complete
Combining these two gates we can make NOR gate which is again a universal gate.

Option(B) : NOR = Functionally Complete
NOR is a universal gate.

So we can conclude that Option(C) is Correct Answer

• A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2^N AND Gates for N input variables, and for M outputs from PLA, there should be M OR Gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms.
• PLAs differ from Programmable Array Logic devices (PALs and GALs) in that both the AND and OR gate planes are programmable.
• Fuses are attached to and- or gate inputs to allow inputs to reach the and - or gates and If fuses don't work , then no input can reach to these gates of PLA

 

• Total programmable fuses= fuses required by AND gates + fuses required by OR gates
• Fuses required by AND gates = 2* no. Of inputs * no. Of and gates = 2*16*32= 1024 fuses
• Fuses required by OR gates = no. Of outputs * no. Of and gates = 8* 32 = 256 ( total outputs should be equal to no. Of OR gates and inputs have to cross AND gates and then goto OR gates)
• Total fuses = 1024+ 256= 1280

Three stage counter with RS Flip Flop is 3 bit counter, so after every 8 clock pulse, it will return to initial state. and in the 9th pulse, the counter stage will exceed by 1
Initial  value of the counter  is 1,
state after 8 clock pulse  counter will be again 1,
So, after 9th clock counter will be again 2

X(A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15) By solving the above K-Map we get X= A+BCD

Adding two numbers
1100 0011
+0100 1100
---------------
10000 1111

Carry in and Carry out of MSB is same, so, There is no overflow.
For overflow  we have condition of C = ( Carryout ⊕ Carry In )
so, Overflow flag = 0,
Carry Flag = 1
Zero Flag = 0
Option (D) is correct

IEEE-754 Format  (−1)^S1.M^E−127
S → sign
M → Mantissa
E → Exponent
Precision can be understood as the maximum accuracy through which a floating point number can be represented.
It is the smallest change that can be represented in floating point representation. The fractional part of a single precision normalized number has exactly 23 bits of resolution, (24 bits with the implied bit).
Precision is represented by ' 1.M ' where M is 23 bits and in total 24 bits are used for representing a précised number .
With 24 bits we can represent  2²⁴ numbers (0−2²⁴−1). What is that value in decimal ?
Largest number that can be represented in any base x is x^{number of digits}−1 (starting from 0).
base X^{number of digits} = base Y^{number of digits}
base X^{number of digits} = base Y^{number of digits}
Binary represented in base 2 and Decimal represented in base 10
So, 2²⁴=10^x
Apply log on both sides, then we get
log₂2²⁴ = log₂10^x
24=xlog₂10
x=7.22
So, correct answer is (C)

Given
Ram chip size = 8K x 4 bits = 2³ x 2¹⁰ x 2² = 2¹⁵ bits
it is given that Bye addressable (2¹⁵/8 Byte) = 2¹² bytes
In Array there are 6*4 =24 chip so to address them we need 5 bit .
So, total number of bits required = 12 + 5 = 17 bits

Q₁Q₀  values are 11,10,01,00

• after 1 = 11
• after 2 = 10
• after 3 = 01
• after 4 = 00

Capacity of memory = 2²¹ bit
So, Capacity of memory in Byte will be = 2²¹/2³ = 2¹⁸ bytes
Given Word size of 4 Byte is
So, number of 4-byte words memory should have = 2¹⁸/ 2² = 2¹⁶ words
RAM chips size = 2K x 8 (means 8 bit word can be store in one cell of RAM),
therefore, RAM capacity = 2¹¹ words.
Number of decoder line required = 2¹⁶/2¹¹ = 2⁵ = 32
5 to 32 Decoder will be required to select the desired row.

• Output of AND Gate will available at the input of Ex-OR gate after (Inverter Time + And Gate) = 6 + 10 = 16 ns
• OR gate will reach to the XOR gate in only 11 ns
• 11ns < 16ns, So the output of OR gate will immediately comes at XOR
• which will cause a glitch to happen for 5 n.
• it Means 16 - 11 = 5 ns more will be required the get the actual output

Option (A)
X.X = X  // 1*1=1 or 0*0=0

Option (B)
(X + Y).X
X.X + X.Y
X + X.Y  // X.X=X
X(1 + Y)
X * 1       // 1+anything =1
X      // 1*anything =anything

Option (C)
X' + XY
(X' + X)(X' + Y)
(1)(X' + Y)  // 1*x=x
(X' + Y)

Option (D)
(X + Y).(X + Z)
X.X + X.Z + X.Y + Y.Z
X(1 + Z + Y) + Y.Z
X + Y.Z

• A switch can store only 1 bit  Either  (0 =OFF)  or (1  =ON)
• It is given that there are 12 switches therefore we have 12 bits
• In Binary Coded Decimal (BCD) Each of the decimal numbers (0-9) is represented by its equivalent binary pattern which is generally of 4-bits.
• It means Each digit of BCD representation takes 4 bits,
• So There will be 12/4 = 3 BCD digits each containing 4 bits
• In Each group maximum 10 numbers can be stored  because A BCD digit can be from 0-9
• So, Different possible BCD numbers in 12 switches are = 10 * 10 * 10 = 1000 = 10³
• It means 10³ BCD numbers can be stored in this 12 Switches

We need to perform add operation (−14)₁₀+(−15)₁₀

(−14)₁₀
+(−15)₁₀
----------------
=(-29)₁₀
-----------------

So, Results which is Negative Number

Representing Negative Number(-29) in 2's complement
Step 1  : Get 1's complement of 29
Step 2 : add 1 to the result

8-Bit Binary representation of 29 = 00011101
1's complement of 29 = 11100010
Now add 1 to it then we get 11100011

F (A, B, C, D) = Σ (0, 1, 2, 8, 9, 12, 13)
d (A, B, C, D) = Σ (10, 11, 14, 15)
By solving the above k-map we get A+B'D'+B'C'

AB+C
= (A+C)(B+C)   //  identity X+YZ=(X+Y)(X+Z)
Now using De-Morgan’s theorem, we have
= (A+C)(B+C)
=(  (  (A+C)(B+C)  )’ )'
= (  (A+C)’ + (B+C)’   )’
So the minimum number of NOR gates required will be 3

(A+C’)(B’+C’) = AB’+C’

Distributive Law – This law permits the multiplying or factoring out of an expression.

• A(B + C) = A.B + A.C (OR Distributive Law)
• A + (B.C) = (A + B).(A + C) (AND Distributive Law)

(632)₈ = (19A)₁₆

Step 1: Look up each octal digit to obtain the equivalent group of three binary digits
(6)₈ = (110)₂
(3)₈ = (011)₂
(2)₈ = (010)₂

Step 2: Group each value of step 1 to make a binary number.
110 011 010
(632)₈ = (110011010)₂

Step 3: Now convert the binary number from step 2 to hexa by grouping all the digits of the binary in sets of four starting from the LSB (far right).
0001 1001 1010
Note: add zeros to the left of the last digit if there aren't enough digits to make a set of four.

Step 4: Convert each group of four to the corresponding hexadecimal
0001=1, 1001=9, 1010=A.
So, the octal 632 is equivalent to 19A in hexadecimal.

The given function is nothing but an EXNOR which is same as BICONDITIONAL.
[⨀≡⇔]

1. Add two BCD numbers using we require 1 half adder 3 full adders
2. In BCD Each digit is represented in 4bit Binary code
3. If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.
4. If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the sum is invalid.
5. To correct the invalid sum, add 0110₂ to the four-bit sum. If a carry results from this addition, add it to the next higher-order BCD digit. ---> for this 1 half adder and  2 full adders

Thus to implement BCD Adder Circuit we require :

• 4-bit binary adder for initial addition(1 half adder(adding of both LSB) 3 full adders(remaining 3 bits for both numbers along with carry))
• Logic circuit to detect sum greater than 9 and
• One more 4-bit adder(1 half adder and  2 full adders) to add 0110₂ in the sum if sum is greater than 9 or carry is 1
• Total 5 Full Adders 2 Half Adders

5

5

First, we can design an AND gate. We can invert it later.

How do we get an AND gate from NOR gates? We can see that (A’ + B’)’ is same as (A.B) , where + represents OR, . represents AND and ' represents complement operation. This is a De Morgan’s law.

We can get the operation of ORing two variables and complementing the result by using a NOR gate. We can also achieve the inverting operating using a NOR gate, just by fusing the two input pins.

• The difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two outputs.
• 
• The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.

In D-flip-flop output is same as input given to the flip-flop. So final output would be 0.
In this question LSB,MSB are 0 so final output will be 0,
Note : Here we don't know about order of input

(2⁶) = 64
So, In order to divide the frequency we need 6 flip flops

• With n bit numbers possible is = 2ⁿ
• Here given n=8 therefore number possible is 2⁸ = 256
• An 8-bit register can store a Unsigned number between 0 and 2⁰ + 2¹ + 2² + 2³ + 2⁴ + 2⁵ + 2⁶ + 2⁷ or 2⁸ − 1, that is, 255
• An 8-bit register can store a  signed number range would be -128 to 127 (0 has two representation)

The excess-3 code (or XS3) is a non-weighted code used to express decimal numbers. It is a self-complementary binary coded decimal (BCD) code and numerical system which has biased representation

Excess-3 codes are unweighted and can be obtained by adding 3 to each decimal digit then it can be represented by using 4 bit binary number for each digit. An Excess-3 equivalent of a given binary binary number is obtained using the following steps:

• Find the decimal equivalent of the given binary number.
• Add +3 to each digit of decimal number.
• Convert the newly obtained decimal number back to binary number to get required excess-3 equivalent.

Odd parity of word can be conveniently tested by XOR gate, since, XOR outputs 1 only when the input has odd number of 1’s.

• The XOR, XNOR, Even Parity, and Odd Parity gates each compute the respective function of the inputs, and emit the result on the output. The two-input truth table for the gates is the following.
• 
• As you can see, the Odd Parity gate and the XOR gate behave identically with two inputs; similarly, the even parity gate and the XNOR gate behave identically. But if there are more than two specified inputs,
• the XOR gate will emit 1 only when there is exactly one 1 input, whereas the Odd Parity gate will emit 1 if there are an odd number of 1 inputs.
• The XNOR gate will emit 1 only when there is not exactly one 1 input, while the Even Parity gate will emit 1 if there are an even number of 1 inputs.

• If J and K are both low then no change occurs.
• If J and K are both high at the clock edge then the output will toggle from one state to the other.
• It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states.
• It can also act as a T flip-flop to accomplish toggling action if J and K are tied together.
• This toggle application finds extensive use in binary counters

Number of flip-flops required to construct a binary modulo N counter is
2^x = N
Where x= ceiling (log₂N)
Given Question we have to construct mod 19
therefore 2^x = 19
x=ceiling (log₂19)
x=4.something
x=5

• Shift Register is a group of flip flops used to store multiple bits of data.
• The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses.
• An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.
• The registers which will shift the bits to left are called “Shift left registers”.
• The registers which will shift the bits to right are called “Shift right registers"
• After Each shift next significant bit moves to LSB and the bit in LSB is read in right shift operation.
• After Each shift next significant bit moves to MSB and the bit in MSB is read in Left shift operation.
• so finally  The last element moves to LSB position after (n-1) shifts i.e, T(n-1) seconds

In computers, subtraction is generally carried out by 2’s complement
With the help of subtraction by 2’s complement method we can easily subtract two binary numbers.

The operation is carried out by means of the following steps:
(i) At first, 2’s complement of the subtrahend is found.
(ii) Then it is added to the minuend.
(iii) If the final carry over of the sum is 1, it is dropped and the result is positive.
(iv) If there is no carry over, the two’s complement of the sum will be the result and it is negative.

• A'.B + A.B' + A.B
• A'.B + A.B + A.B'
• B(A' + A) + A.B'  // Taking B as common
• B + A.B'
• (B+A).(B+B') // Distributive Law
• (B+A).1   // (0+1=1) or (1+0=1)
• B+A  // 1.anything=anything

only Option(B) is correct

(i) wx + w(x + y) + x(x + y)= x + wy
wx + w(x+y) +x(x+y)
= wx + wx + wy + x + xy
= wx + wy + x + xy
= x(w+y+1) + wy  // taking x as common
= x+wy   // 1+anything=1

(ii) (wx’(y + xz’) + w’x’)y = x’y
(wx’(y+xz’)+w’x’)y
= wx’y + wx'xz'+ w’x’y
= wx’y + w’x’y  // x'x = 0
= x’y(w+w')
= x’y

Option(A): Every logic network is equivalent to one using just NAND gates or just NOR gates :  True
NAND gate and NOR gates are universal gates by using these we can construct anything

Option(B):Boolean expressions and logic networks correspond to labelled acyclic digraphs : True
Refer : https://en.wikipedia.org/wiki/Propositional_directed_acyclic_graph

Option(C) and (D) : False
An atom of a Boolean algebra is an element x such that there exist exactly two elements y satisfying y ≤ x, namely x and 0. A Boolean algebra is said to be atomic when every element is a sup of some set of atoms (the bottom element is always the empty sup).

Every finite Boolean algebra is atomic, and moreover isomorphic to the power set 2^X of the set X of its atoms, under the operations of union, intersection, and complement, with 0 and 1 realized by respectively the empty set and X. Conversely every finite power set forms a Boolean algebra under union, intersection, and complement

Schematic Diagram of 2 to 1 Multiplexer using Logic Gates
A MUX need AND gates equal to the number of input channels, NOT gates equal to the number of Control signals and a single OR gate.

The equation of digital multiplexer is given by
Y_output =D₀(S₀)'+D₁S0
Here firstly we have to solve two AND operations followed by one OR operation

Given output f = (x + x') + (y + y') = (x + y) + (x' + y')

 (x + y) + (x' + y')  is  rewriting the given solution keep in mind that known output will be (x + y)(OR gate)

(x + y) is coming from OR gate
(x'+ y') is output of a gate by using the inputs x and y
This is possible only when the ? marked box is a NAND gate.

w' + w'z + z'xy
= w'(1 + z) + z'xy
= w' + z'xy
Gate number 2 which produces w'z is redundant as it has been eliminated in final result
So, option (B) is correct

BASIS FOR COMPARISON	SRAM	DRAM
Speed	Faster	Slower
Size	Small	Large
Cost	Expensive	Cheap
Used in	Cache memory	Main memory
Density	Less dense	Highly dense
Construction	Complex and uses transistors and latches.	Simple and uses capacitors and very few transistors.
Single block of memory requires	6 transistors	Only one transistor.
Charge leakage property	Not present	Present hence require power refresh circuitry
Power consumption	Low	High

we have 3 elements in a 32-bit floating point representation :
(i) Sign
(ii) Exponent
(iii) Mantissa
Sign bit is the first bit(MSB) of the binary representation. '1' implies negative number and '0' implies positive number.
Exponent is decided by the next 8 bits of binary representation.
Mantissa is calculated from the remaining 23 bits of the binary representation. It consists of '1' and a fractional part

According to DeMorgan’s second theorem, a NOR gate is equivalent to a bubbled AND gate.
The Boolean expressions for the bubbled AND gate can be expressed by the equation shown below.

• For NOR gate, the equation is:  Z=(A+B)'
• For the bubbled AND gate the equation is:  Z= (A'.B')

As the NOR and bubbled gates are interchangeable, i.e., both gates have exactly identical outputs for the same set of inputs.

• Therefore, the equation can be written as shown below :  (A+B)'=A'.B'-------(1)
• This equation (1) or identity shown above is known as DeMorgan’s Theorem.
• The symbolic representation of the theorem is shown in the figure below:

IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

Note:

• There are several types of De-multiplexers based on the output configurations such as 1:4, 1:8 and 1:16.
• These are available in different IC packages and some of the most commonly used de-multiplexer ICs includes 74139 (dual 1:4 DEMUX), 73136 (1:8 DEMUX), 74154 (1:16 DEMUX), 74159 (1:16 DEMUX open collector type), etc.

EX-OR  return 1 when inputs are different otherwise 0  i.e, for same input it return 0
(A)1 ⊕ 0 = 1         //  True because different input
(B) 1 ⊕ 1 ⊕ 1 = 1  //  True  1 ⊕ 1 =0 and 0 ⊕ 1 =1
(C) 1 ⊕ 1 ⊕ 0 = 1  // False  1 ⊕ 1 =0 and 0 ⊕ 0 =0
(D) 1 ⊕ 1 = 0      // True  because Same  input

In Ripple Carry Adder :

• Each full adder has to wait for its carry-in from its previous stage full adder.
• Thus, n^th full adder has to wait until all (n-1) full adders have completed their operations.
• This causes a delay and makes ripple carry adder extremely slow.
• The situation becomes worst when the value of n becomes very large.
• To overcome this disadvantage, Carry Look Ahead Adder comes into play.

Carry Look Ahead Adder :

• Carry Look Ahead Adder is an improved version of the ripple carry adder.
• It generates the carry-in of each full adder simultaneously without causing any delay.
• The time complexity of carry look ahead adder = Θ (logn).
• The working of carry look ahead adder is based on the principle:The carry-in of any stage full adder is independent of the carry bits generated during intermediate stages.

• Sequential circuit contains a set of inputs and outputs S .
• The outputs s of sequential circuit depends not only on the combination of present inputs but also on the previous outputs s.
• Previous output is nothing but the present state. Therefore, sequential circuits contain combinational circuits along with memory storage elements.
• Some sequential circuits may not contain combinational circuits, but only memory elements.

• In a ripple counter using edge-triggered JK flip-flops the pulse input is applied to clock input of one flip flop then
• First Flip flop is clocked and the rest are clocked from their previous flip flop's output.

above diagram is 3 bit ripple counter using JK flip flop Here you can see in diagram Q0,Q1 applied to clock input of one flip flop

Maximum 30 digit decimal number = 10³⁰ – 1
Maximum x bit binary number = 2^x – 1
10³⁰ – 1 = 2^x – 1
Apply log on both then we get
log ₂10³⁰ = x
x = 30 log ₂10
x = 30 x 3.3
x = 99
Therefore minimum 99 bits we require  to represent 30 digit number

FD​₁₆ - ​88₁₆

• FD​₁₆=(253)₁₀
• 88₁₆=(136)₁₀

Therefore (253)₁₀ - (136)₁₀ = (117)₁₀
Now represent (117)₁₀ in Hexadecimal :
(117)₁₀ = (75)₁₆

We need 1 Mbytes, i.e., 1 x 2²⁰ x 8 bits.
We have RAM chips of capacity 256 Kbits = 2⁸ x 2¹⁰bits.
Total number of RAM chip = Total size /1 RAM size
(2²⁰ x 2³ bits.)/(2⁸ x 2¹⁰bits.) =2⁵ = 32

Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, SRAM does not have to be periodically refreshed but DRAM periodically refreshed 

BASIS FOR COMPARISON	SRAM	DRAM
Speed	Faster	Slower
Size	Small	Large
Cost	Expensive	Cheap
Used in	Cache memory	Main memory
Density	Less dense	Highly dense
Construction	Complex and uses transistors and latches.	Simple and uses capacitors and very few transistors.
Single block of memory requires	6 transistors	Only one transistor.
Charge leakage property	Not present	Present hence require power refresh circuitry
Power consumption	Low	High