# Digital Logic Design | Subject Wise

## Digital Logic Design | Subject wise

 Question 1
A computer uses ternary system instead of the traditional binary system. An n bit string in the binary system will occupy
 A 3+n ternary digits B 2n/3 ternary digits C N(log23) ternary digits D N(log32 ) ternary digits
Question 1 Explanation:
Maximum Binary Numbers Possible using n-bit   =  2n -1
Maximum Ternary  Numbers Possible using x-bit in = 3x -1
Ternary and Binary take different Number of bits to represent same number.
i.e, Maximum value representable in ternary system using x digits = Maximum value representable in binary system using  n digits
3x -1 =  2n -1
3=  2n
Now, taking log on both side :
X= log3 ( 2 )
X=n*log32
 Question 2
In the diagram above, the inverter (NOT gate) and the AND-gates labelled 1 and 2 have delays of 9, 10 and 12 nanoseconds(ns), respectively. Wire delays are negligible. For certain values of a and c, together with the certain transition of b, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of the glitch is A 7ns B 9ns C 11ns D 13ns
Question 2 Explanation:
• Output of AND gate 1 will be available at the input of OR gate after (Inverter Time and AND gate1 Time) = 9+10 = 19ns
• It means AND gate 1 will take = 9+10 = 19ns
• Output of AND gate 2 will be available at the input of OR gate after(only AND gate2 Time) = 12 ns
• A Glitch will be generated for (AND gate1 Time)-(AND gate2 Time) = 19-12 = 7ns
 Question 3
Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is not complete?
 A { AND, OR } B { AND, NOT } C { NOT, OR } D { NOR }
Question 3 Explanation:
• NOR and NAND are the universal gates
• Any logic gate can be implemented by using these NOR and NAND logic gates.
• NOR and NAND are Functionally Complete
Option(A) : {AND, OR}
These two gates do not make a universal gate they are just Basic gates.

Option(B) : {AND, NOT} = NAND = Functionally Complete
Combining these two gates we can make NAND gate which is again a universal gate.

Option(C) : {NOT, OR}} = NOR = Functionally Complete
Combining these two gates we can make NOR gate which is again a universal gate.

Option(D) : NOR = Functionally Complete
NOR is a universal gate.

So we can conclude that Option(A) is Correct Answer
 Question 4
If a variable can take only integral values from 0 to n, where n is an integer, then the variable can be represented as a bit field whose width is (the log in the Solutions are to the base 2, and [log n] means the floor of log n)
 A [log(n)] + 1 bits B [log (n-1)) + 1 bits C [log (n+1)] + 1 bits D None of the above
Question 4 Explanation:
Suppose a number 128 is to represented as a bit-field then its width would be [log2(n)] + 1
Therefore, ((log2 128) + 1) = 7 + 1 = 8 bits are required to represent 128
Note : A number of the form 2x has x+1 bits.
Thus any number chosen in between (0,n] should have [log2 (n)]+1 bits.
 Question 5
Given √(224)r = 13r the value of radix r is
 A 10 B 8 C 6 D 5
Question 5 Explanation:
Given
√(224)r = (13)r
Squaring both sides
(√(224)r)2= ((13)r)2

Above  equation can be written as: (224)r = ((13)r)2
Converting to decimal number:
2r2 + 2r1 + 4r0 = (1r1 + 3r0)2
2r2 + 2r + 4 = (r + 3)2
r2 - 4r - 5 = 0
r2 - 5r  + r - 5 = 0
⟹(r−5)(r+1)=0

Root of the above equation is 5, -1.
r being a base, it can not be −1.

• radix r =10,  13 is not the root of 224
• radix r =8,  224r = (64*2+8*2+4) =128+20 =148  (not a perfect square)
• radix r =6,  224r = (36*2+6*2+4) =72+16 =88 ( not a perfect square)
•  radix r =5, 224r = (25*2+5*2+4) =50+14 =64 (perfect square) i.e,√64 =8 =(13)5
 Question 6
The Boolean expression Y = (A + B' + A'B)C' is given by
 A AC' B BC' C C' D A
Question 6 Explanation:
y=(a+b'+a'b)c'
y=[a+(b'+a')(b'+b)]c' ∴ distributive law
y=[a+(b'+a').1]c'  ∴ b'+b=1
y=(a+b'+a')c'
y=(a+a'+b')c'
y=(1+b')c'          ∴a+a'=1
y=c'                   ∴1+b'=1 Question 7
 A (( A + B )’ +C ) ( D’E’ )) B (( A + B )’ + C ) ( DE’ )) C ( A + ( B + C )’ ) ( D’E ) D ( A + B + C’ ) ( D’E’ )
 Question 8
 A Full adder B Full subtractor C Shift register D Decade counter
Question 8 Explanation:
Implement Full Subtractor using 2 half Subtractors and one OR gate :
• Full Subtractor using 2 half Subtractors and one OR gate as follow:
• The foremost disadvantage of the half subtractor is, we cannot make a Borrow bit in this subtractor. Whereas in its design, actually we can make a Borrow bit in the circuit and can subtract with the remaining two i/ps.
• Here A is minuend, B is subtrahend & Bin is borrow in. The outputs are Difference (Diff) & Bout (Borrow out). The complete subtractor circuit can obtain by using two half subtractors with an extra OR gate. Implement Full Subtractor using 2 half Subtractors and one OR gate as follow : Below circuit can be done with two half-Subtractor circuits. In the initial half-Subtractor circuit, the binary inputs are A and B. It will generate two outputs namely difference (Diff) & Borrow. • The difference o/p of the left subtractor is given to the Left half-Subtractor circuit’s. Diff output is further provided to the input of the right half Subtractor circuit. We offered the Borrow in bit across the other i/p of the next half subtractor circuit. Once more it will give Diff out as well as Borrow out the bit. The final output of this subtractor is Diff-output.
• On the other hand, the Borrow out of both the half Subtractor circuits is connected to OR logic gate. Later than giving out OR logic for two output bits of the subtractor, we acquire the final Borrow out of the subtractor. The last Borrow out to signify the MSB (a most significant bit).

 Question 9
When two numbers are added in excess-3 code and the sum is less than 9, then in order to get the correct answer it is necessary to
 A Subtract 0011 from the sum B Add 0011 to the sum C Subtract 0110 from the sum D Add 0110 to the sum
Question 9 Explanation:
In Excess-3 code
• If a carry is there = Add 3 with the result
• No carry = Subtract 3 from the result
• For 9  it does not produce the carry, Hence 0011(3) will be subtracted from sum to get actual value of BCD.
 Question 10
The characteristic equation of an SR flip-flop is given by
 A Qn+1 = S + RQn B Qn+1= RQ’n + SQn C Qn+1= S’ + RQn D Qn+1 = S + R’Qn
Question 10 Explanation:
1. SR Flip flop: Qnext = S+R'Q
2. JK Flip flop: Qnext =JQ'+ K'Q
3. D Flip flop Qnext = D
4. T Flip flop Qnext = T ⊕  Q Question 11
By using an eight-bit optical encoder the degree of resolution that can be obtained is (approximately)
 A 1.8o B 3.4o C 2.8o D 1.4o
Question 11 Explanation:
The optical encoder is a transducer commonly used for measuring rotational motion. It consists of a shaft connected to a circular disc, containing one or more tracks of alternating transparent and opaque areas.

An optical encoder has several tracks, with different patterns on each, to produce a binary code output that is unique for each encoded position. There is a track for each output bit, so an 8-bit absolute encoder has 8 tracks, 8 outputs and 256 output combinations, for a resolution of 360/256 = 1.4°.
 Question 12
The number of digit 1 present in the binary representation of 3 × 512 + 7 × 64 + 5 × 8 + 3
 A 8 B 9 C 10 D 12
Question 12 Explanation:
3 x 512 + 7 x 64 + 5 x 8 + 3

= (2 + 1) x 29 + (4 + 2 + 1)26 + (4 + 1)23 + (2 + 1)

= 210 + 29 + 28 + 27 + 26 + 25 + 23 + 21 + 1

= 210 + 29 + 28 + 27 + 26 + 25 + 23 + 21 + 20

=11111101011

Note : 210 (10 0's followed by 1) , 29 (9 0's followed by 1) ..  ..  ..  ....  ..

Therefore Total Number of 1's =9
 Question 13
0.75 decimal system is equivalent to ____ in octal system
 A 0.6 B 0.52 C 0.54 D 0.5
Question 13 Explanation:
(0.75)10 = (0.110)2 = (0.60)8
The Octal equivalent of (0.75)10= (0.60)8
 Question 14
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
 A Q = 0, Q’ = 1 B Q = 1, Q’ = 0 C Q = 1, Q’ = 1 D Indeterminate states
Question 14 Explanation:

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0 lead to a forbidden state
forbidden state Means  State is invalid state and must not be entered and Not sure of the output and Output changes continuously
This is different from an indeterminate state which means a state where we are not sure of the output.
This is different from an a toggling state where the output changes continuously.

Source : Morris Mano  When both R and S are set as 0, we will get both Q and Q’ as 1. This output will be permanent and it is not dependent on any order of occurrence it only depends on the input values [NO RACE CONDITION].

But after this state if we make R=S=1, the output will be indeterminate depending on which NAND gate processes first (either Q or Q’ will become 0 but we can’t determine which [RACE CONDITION] and it will lead to an indeterminate state.
 Question 15
Ring counter is analogous to
 A Toggle Switch B Latch C Stepping Switch D S-R flip flop
Question 15 Explanation:
A ring counter is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.  for each clock pulse, counter advances switch by one step like in sequential gating systems. So, it works similar as a Stepping Switch.

There are two types of ring counters:
• straight ring counter, also known as a one-hot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
• twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.
Reference : https://en.wikipedia.org/wiki/Ring_counter
 Question 16
The output 0 and 1 level for TTL Logic family is approximately
 A 0.1 and 5V B 0.6 and 3.5 V C 0.9 and 1.75 V D -1.75 and 0.9 V
Question 16 Explanation:
TL gates operate on a nominal power supply voltage of 5 volts, +/- 0.25 volts. Ideally, a TTL “high” signal would be 5.00 volts exactly, and a TTL “low” signal 0.00 volts exactly.

However, real TTL gate circuits cannot output such perfect voltage levels, and are designed to accept “high” and “low” signals deviating substantially from these ideal values.

“Acceptable” input signal voltages range from 0 volts to 0.8 volts for a “low” logic state, and 2 volts to 5 volts for a “high” logic state.

“Acceptable” output signal voltages (voltage levels guaranteed by the gate manufacturer over a specified range of load conditions) range from 0 volts to 0.5 volts for a “low” logic state, and 2.7 volts to 5 volts for a “high” logic state:
 Question 17
Consider a computer system that stores a floating-point numbers with 16-bit mantissa and an 8-bit exponent, each in two’s complement. The smallest and largest positive values which can be stored are
 A 1 × 10-128 and 215× 1015 B 1 × 10-256 and 215× 10255 C 1 × 10-128 and 215× 10127 D 1 × 10-128and 215– 1 × 10127
Question 17 Explanation:
Representation of Floating point number will be = -1S x M x 2E
Given
Mantissa = 16 bit
Exponent = 8 bit

LARGEST NUMBER
LARGEST NUMBER means it should be largest positive number it consists of both largest positive Mantissa and Exponent
• Given mantissa is 16-bit so largest positive mantissa value possible is 0111 1111 1111 1111 (+215-1 in 2's complement)
• Given exponent is 8-bit so largest positive exponent value possible is 0111 1111 (+27-1 (+127) in 2's complement)
Finally largest positive number is (+215-1) x 2127

SMALLEST NUMBER
• Given mantissa is 16-bit so Smallest mantissa value is 0000 0000 0000 0000( 1 is present always at rightmost always 1) = 1
• Given exponent is 8-bit so Largest negative exponent value is (smallest exponent value is) 1111 1111 (-27 (-128) in 2's complement)
Finally smallest positive number is (1 x 2-128)

Note : Exponents are given as power of 10. in the options it should be 2
 Question 18
In comparison with static RAM memory, the dynamic RAM memory has
 A Lower bit density and higher power consumption B Higher bit density and higher power consumption C Lower bit density and lower power consumption D Higher bit density and lower power consumption
Question 18 Explanation:
BASIS FOR COMPARISON SRAM DRAM
Speed Faster Slower
Size Small Large
Cost Expensive Cheap
Used in Cache memory Main memory
Density Less dense Highly dense
Construction Complex and uses transistors and latches. Simple and uses capacitors and very few transistors.
Single block of memory requires 6 transistors Only one transistor.
Charge leakage property Not present Present hence require power refresh circuitry
Power consumption Low High
 Question 19
The Hexadecimal equivalent of 01111100110111100011 is
 A CD73E B ABD3F C 7CDE3 D FA4CD
Question 19 Explanation:
Given Binary Number = 01111100110111100011
Split into 4 term each then we get a Hexadecimal Question 20
One approach to handling fuzzy logic data might be to design a computer using
ternary (base-3) logic so that data could be stored as “true,” “false,” and “unknown.”
If each ternary logic element is called a flit, how many flits are required to represent at least 256 different values?
 A 4 B 5 C 6 D 7
Question 20 Explanation:
• In order to Represent 256 in Binary we require 8 bits  i.e, log2 (256) = 8 bits.
• Similarly in Ternary representation, we require 5 bits i.e, log3 (256) ≈ 5.047 bits
• Now rounding off to the upper integer (since number of bits is an integer) and we get 6
• So Answer should be 6 Flits(Bits)(256=1001113)
 Question 21
How many 128×8 bit RAMs are required to design 32K×32 bit RAM?
 A 512 B 1024 C 128 D 32
Question 21 Explanation:
We need 32K×32 bit RAM
We have RAM chips capacity 128×8 bit
Number of RAMs required = (32 * K * 32) / 128 * 8
Number of RAMs required = (25 * 210 * 25 ) / ( 27 * 23)  ∴ k=210
Number of RAMs required = 220 / 210
Number of RAMs required = 1024
 Question 22
What is the minimum number of two-input NAND gates used to perform the function of two input OR gate
 A One B Two C Three D Four
Question 22 Explanation:
NAND and NOR gates are universal gates. By using of these gates we can realize any gate.

Minimum 3 NAND gates are required to implement an OR gate = A+B = ((A + B)')' = ( A' .B' )'  Question 23
When two n-bit binary numbers are added the sum will contain at the most
 A N bits B (n+3) bits C (n+2) bits D (n+1) bits
Question 23 Explanation:
When two n-bit binary numbers are added the sum will contain at the most (n+1) bits

Example : add 2 decimal numbers let say 3 + 3 equivalent binary representation will be (11)2 +(11)2 Question 24
The 2-input XOR has a high output only when the input values are
 A Low B High C Same D Different
 Question 25
(1217)8 is equivalent to
 A (1217)16 B (028F)16 C (2297)1o D (0B17)16
Question 25 Explanation:
Given number is in base 8 thus each digit can be represented in three binary bits to get overall binary equivalent.
1 => 001
2 => 010
1 => 001
7 => 111
so 16 digit binary equivalent of 1217 is
001 010 001 111
now group it to four digit number
0010 1000 1111
which is (2 8 F)16

(1217)8 = (001 010 001 111)= (0010 1000 1111) = (28F)16
 Question 26
Advantages of synchronous sequential circuits over asynchronous one is
 A Lower hardware requirement B Better noise immunity C Faster operation D None of the above
Question 26 Explanation:
None of the above
 Question 27
The Boolean theorem AB + A’C + BC = AB + A’C corresponds to
 A (A + B) ∙ (A’ + C) ∙ (B + C) = (A + B) ∙ (A’ + C) B AB + A’C + BC = AB + BC C AB + A’C + BC = (A + B) ∙ ( A ‘+ C) ∙ (B + C) D (A + B) ∙ (A’ + C) ∙ (B + C) = AB + A’C
Question 27 Explanation: Question 28
 A X0X1X2 … Xn + X1X2 … Xn + X2X3 … Xn + ⋯ + Xn B X0X1 + X2X3 + … Xn-1 Xn C X0 + X1 + X2 + … + Xn D X0X1 + X3 … Xn−1 + X2X3 + X5 … Xn−1 + ⋯ + Xn−2Xn−1 + Xn E None
Question 28 Explanation: Question 29
If N2 = (7601)8 where N is a positive integer, then the value of N is
 A (241)5 B (143)6 C (165)7 D (39)16
Question 29 Explanation:
N2 = (7601)8
N2 = 7 * 83 + 6*82+ 0*81 + 1*80
N2 = 7*8*8*8 + 6*8*8 + 0 + 1*8
N2 = 3969
N = (63)10

Now consider the option

(241)5 = 2*5*5 + 4*5 + 1 = 71
Option (A) is incorrect.

(143)6 = 1*6*6 + 4*6 + 3 = 63
Option (B) is correct.

(165)7 =  1*7*7 + 6*7 +5 = 95
Option (C) is incorrect.
 Question 30
If (12x)3 = (123)x then the value of x is
 A 3 B 3 or 4 C 2 D None of these
Question 30 Explanation:
we know that Radix > digit
• From LHS : (12x)3 tells us that the value of x should be less than 3
• From RHS : (123)x tells us that the value of x should be greater than 3 because  largest digit among 123 is 3.
 Question 31
A computer uses 8 digit mantissa and 2 digit exponent. If a = 0.052 and b = 28E + 11 then b + a – b will
 A Result in an overflow error B Result in an underflow error C Be 0 D Be 5.28 E + 11
Question 31 Explanation:
Given that
Computer uses 8 digit mantissa and 2 digit exponent :

In standard form : a = 0.052 = 0.52 E-1;  mantissa = 0.52,exponent = −1.
it means a=0.052 can be represented in M*E by a = 0.052 = 0.52 * 10-1

In standard form : b = 28E+11 =0.28 E+13; mantissa = 0.28, exponent = 13.
it means b= 28E+11 can be represented in M*E by b = 28E+11 = 0.28*1013

To add b+a, Small exponent number (a) is shifted to (13-(-1) =14) Therefor 14 places to right side
a = 0.0000000000000052E+13.

But, computer uses only 8 digit mantissa,
digits beyond 8th position will be discarded.

So a = 0.00000000E+13 = 0.0 E+13
b + a = (0.28E + 13) + (0.0E + 13 ) = 0.28E + 13
Then b + a - b = (0.28E + 13) - (0.28E + 13) = 0
 Question 32
The Boolean expression ( A + C’)(B’+ C’) simplifies to
 A C’ + AB’ B C’ (A’ + B) C B’C’ + AB’ D None of these.
Question 32 Explanation:
Given Boolean expression ( A + C’)(B’+ C’)
(A+C')(B'+C')
AB'+AC'+BC'+C'
AB'+(A+B+1)C'  //taking C' common
AB'+(1)C' // A+1=1
We Know ( 1*C' =C')
So required expression AB'+C' .
 Question 33
In the expression A'(A’ + B’) by writing the first term A as A + 0, the expression is best simplified as
 A A + AB B AB C A' D A + B
Question 33 Explanation:
A'(A’ + B’)
= A'A' + A'B'
= A' + A'B' // A*A=A
= A'(1 + B') // Taking A' as common
= A'(1) // 1 + B' = 1
= A' // A*1=A
 Question 34
The logic operations of two combinational circuits in Figure-I and Figure-II are A Entirely different B Identical C Complementary D Dual
Question 34 Explanation: Figure : 1 = x'y'
Figure : 2 = xy'
Entirely different
 Question 35
 A 1 B 0 C X D X’
Question 35 Explanation:
IN EX-OR output is 1 When inputs are different otherwise 0
• 0 XOR 0 =0
• 0 XOR 1 =1
• 1 XOR 0 =1
• 1 XOR 1 =0
In the above function implemented with Ex-OR Gate and both the inputs of the first Ex-OR gate are set to 0. Then the output is also 0 the further two gates are also getting 0 as both their inputs

The function continue to generate 0
 Question 36
Which of the following is not a valid rule of XOR?
 A 0 XOR 0 = 0 B 1 XOR 1 = 1 C 1 XOR 0 = 1 D B XOR B = 0
Question 36 Explanation:
IN EX-OR output is 1 When inputs are different otherwise 0

TRUTH TABLE
• 0 XOR 0 =0
• 0 XOR 1 =1
• 1 XOR 0 =1
• 1 XOR 1 =0

 Question 37
Which of the following is termed as minimum error code
 A Binary code B Gray code C Excess 3 code D Octal code
Question 37 Explanation:
• The gray code which is also known as the reflected binary code is a binary numeral system where two successive values differ in only one bit position at a time.
• Gray codes are less error-prone for mechanical devices that involve making and breaking electrical circuits because they only change in one bit position at a time.
• Gray code  considered as the minimum error code.
 Question 38
Repeated execution of simple computation may cause compounding of
 A Round-off errors B Syntax errors C Run-time errors D Logic errors
Question 38 Explanation:
Roundoff error is the difference between an approximation of a number used in computation and its exact (correct) value. In certain types of computation, roundoff error can be magnified as any initial errors are carried through one or more intermediate steps and repeated execution.
 Question 39
How many 2-input multiplexers are required to construct a 210 input multiplexer?
 A 1023 B 31 C 10 D 127
Question 39 Explanation:
To construct 210 x 1-MUX using 2x1 MUX:

1024/2 = 512
512/2=256
256/2=128
128/2=64
64/2=32
32/2=16
16/2=8
8/2=4
4/2=2
2/2=1

Now add all the values  512+256+128+64+32+16+8+4+2+1=1023 MUX

Outcome from the question : In general, The number of N-input Multiplexers needed to create a M-input multiplexer (M > N) is, Question 40
The range of integers that can be represented by n bit 2’s complement number system is:
 A -2n-1 to (2n-1 – 1) B -(2n-1 – 1)to (2n-1 – 1) C -2n-1 to (2n-1 ) D -(2n-1 + 1)to (2n-1 – 1)
Question 40 Explanation:

For n bit 2’s complement numbers, range of number is -(2(n-1)) to +(2(n-1)-1)
• Number of distinct numbers that can be represented using n bits = 2n
• In Unsigned numbers these corresponds to numbers from 0 to 2n−1.
• In Signed numbers in 1′s complement or sign magnitude representation, these corresponds to numbers from −(2n−1−1) to ( 2n−1 −1 )   with 2 separate representations for 0.)
• In Signed numbers in 2′s complement representation, these corresponds to numbers from (−2n−1 ) to (2n−1 −1 )   with a single representation for 0.
 Question 41
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2’s complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be
 A 1, 1, 0 B 1, 0, 0 C 0, 1, 0 D 1, 0, 1
Question 41 Explanation:
Both numbers are given in 2’s complement form.

01001101
+11101001
—————
100110110

Carry flag =1,
Overflow flag = 0,
Sign bit = 0

Note :
In 2′s complement addition Overflow happens only when:
• Sign bit of two input numbers is 0, and the result has sign bit 1
• Sign bit of two input numbers is 1, and the result has sign bit 0.
When two unsigned numbers are added, overflow occurs if
• there is a carry out of the leftmost bit.
 Question 42
The two numbers given below are multiplied using the Booth’s algorithm
• Multiplicand: 0101 1010 1110 1110
• Multiplier: 0111 0111 1011 1101
How many additions/subtractions are required for the multiplication of the above two numbers?
 A 6 B 8 C 10 D 12
Question 42 Explanation: Question 43
The addition of 4-bit, two’s complement, binary numbers 1101 and 0100 results in
 A 0001 and an overflow B 1001 and no overflow C 0001 and no overflow D 1001 and an overflow
Question 43 Explanation:
Both numbers are given in 2’s complement form.
1101 (-3)
0100 (4)
-------
0001 (1)

It is -3+4=1, so no overflow
carry bit =1

Note :
In 2′s complement addition Overflow happens only when:
• Sign bit of two input numbers is 0, and the result has sign bit 1
• Sign bit of two input numbers is 1, and the result has sign bit 0.
When two unsigned numbers are added, overflow occurs if
• there is a carry out of the leftmost bit.
 Question 44
The switching expression corresponding to F(A,B,C,D)= Σ(1,4,5,9,11,12) is:
 A BC’D’ + A’C’D + AB’D B ABC’ + ACD + B’C’D C ACD’ + A’BC’ + AC’D’ D A’BD + ACD’ + BCD’
Question 44 Explanation:
f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) On solving above k-map we get BC’D’ + A’C’D + AB’D
 Question 45
Consider the following boolean function of four variables,
f (w, x, y,z) = Σ(1, 3, 4, 6, 9, 11, 12, 14],
the function is
 A Independent of one variable B Independent of two variables C Independent of three variables D Dependent on all variables
Question 45 Explanation:
F (w, x, y,z) = Σ(1, 3, 4, 6, 9, 11, 12, 14] On solving K-MAP we get ZX’+XZ’
therefore  it is independent of w,y
it means w,y are not required to represent above function f
 Question 46
The minimum number of NAND gates required to implement the Boolean function A + AB’+ AB’C is equal to
 A 0 B 1 C 4 D 7
Question 46 Explanation:
A + AB' + AB'C
A + AB'(1 + C)
A + AB'
A(1 + B')
A

So no NAND gate required
 Question 47
 A AB + AC + BC B A + BC C A + B D A + B + C
Question 47 Explanation: A(B+C) + AB + (A+B)C
AB+AC+AB+AC+BC
AB+AC+BC
 Question 48
For a binary half-subtractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (=borrow) are
 A D = AB + A’B , X = A’B B D = A’B + AB’ , X = AB’ C D = A’B + AB’ , X = A’B D D = AB + A’B , X = AB’
Question 48 Explanation:  Question 49
Consider the following gate network Which one of the following gates is redundant?
 A Gate No. 1 B Gate No. 2 C Gate No. 3 D Gate No. 4
Question 49 Explanation:
w' + w'z + z'xy
= w'(1 + z) + z'xy
= w' + z'xy
Gate number 2 which produces w'z is redundant as it has been eliminated in final result
So, option (B) is correct
 Question 50
The dynamic hazard problem occurs in
 A Combinational circuit alone B Sequential circuit only C Both (a) and (b) D None of the above
Question 50 Explanation:
• Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays. Hazards occur in combinational circuits, where they may cause a temporary false output value. When they occur in asynchronous sequential circuits hazards may result in a transition to a wrong stable state.
• When the output changes several times then it should change from 1 to 0 or 0 to 1 only once, it is called "dynamic hazard".
• Dynamic hazard occur when the output changes for two adjacent input combinations while changing, the output should change only once. But it may change three or more times in short intervals because of different delays in several paths. Dynamic hazards occur only in multilevel circuit.
 Question 51
The logic circuit given below converts a binary code y1,y2,y3 into A Excess-3 code B Gray code C BCD code D Hamming Code E NONE
Question 51 Explanation:
X1 = Y1
X2= Y1⊕Y2
X3=X2⊕Y3=Y1⊕Y2⊕Y3
NONE OF THE MATCHING
 Question 52
 A An oscillating circuit and its output is a square wave B The one whose output remains stable in ‘1’ state C The one having output remains stable in ‘0’ state D Has a single pulse of three times propagation delay
Question 52 Explanation:
If we give the input 0 then we get Output  1
And then it (1) feedbacks to circuit again as input which will generate 0.
So it keep on oscillating between 0-1-0-1-0-1-0-1-0-1.....
Given circuit is logically equivalent to square wave.
option(D) is not correct because input and output are not same .Delay should have been ok if output would have been same with input.
 Question 53
If 12A7C16 = X8, then the value of X is
 A 224174 B 425174 C 6173 D 225174
Question 53 Explanation:
Step 1 : convert into Binary
Step 2 : Make 3 bits into single group from LSB to MSB
Step 3 : Append 0's in the last block as MSB's if sufficient bits are not there

Given (12A7C)16
(12A7C)16= (0001 0010 1010 0111 1100)2
(12A7C)16= (000 010 010 101 001 111 100)2
(12A7C)16= (0225174)8
 Question 54
The Excess-3 code is also called
 A Cyclic Redundancy Code B Weighted Code C Self-Complementing Code D Algebraic Code
Question 54 Explanation:
The excess-3 code (or XS3) is a non-weighted code used to express decimal numbers. It is a self-complementary binary coded decimal (BCD) code and numerical system which has biased representation

Excess-3 codes are unweighted and can be obtained by adding 3 to each decimal digit then it can be represented by using 4 bit binary number for each digit. An Excess-3 equivalent of a given binary binary number is obtained using the following steps:
• Find the decimal equivalent of the given binary number.
• Add +3 to each digit of decimal number.
• Convert the newly obtained decimal number back to binary number to get required excess-3 equivalent.
 Question 55
The simplified SOP (Sum of Product) form the Boolean expression
(P + Q’ + R’)(P + Q’ + R)(P + Q + R’)
 A (P’Q + R) B (P + Q’R’) C (P Q’ + R ) D (PQ + R)
Question 55 Explanation:
Given  (P + Q’ + R’) . (P + Q’ + R) . (P + Q + R’)
(P+Q'+R')=011=3
(P+Q'+R)=010=2
(P+Q+R')=001=1
π=(1,3,2) = (0,4,5,6,7) From the above K-map, POS form is :
P + Q’.R’
 Question 56
Which of the following binary number is the same as its 2’s complement?
 A 1010 B 0101 C 1000 D 1001
Question 56 Explanation:
• In 1’s complement  transforming the 0 bit to 1 and the 1 bit to 0.
• 2’s complement  add 1 to the 1’s complement of the binary number.
a) 1010
• 1's complement = 0101
• 2's complement = 0110
b) 0101
• 1's complement = 1010
• 2's complement = 1011
c) 1000
• 1's complement = 0111
• 2's complement =1000
d) 1001
• 1's complement = 0110
• 2's complement = 0111
Hence Option(c) 1000 is correct.
 Question 57
The functional difference between SR flip-flop and JK flip-flop is that
 A JK Flip-flop is faster than SR flip-flop B JK flip-flop has a feedback path C JK flip-flop accepts both inputs 1 D None of them
Question 57 Explanation:
JK Flip Flop accepts both inputs 1,1 which is not accepted by SR Flip Flop (it gives invalid output) Question 58
Evaluate (X XOR Y) XOR Y?
 A All 1’s B All 0’s C X D Y
Question 58 Explanation:
(X⊕Y)⊕Y = (X⊕Y)'Y+(X⊕Y)Y'
(X⊕Y)⊕Y = (XY+X'Y')Y + (XY'+X'Y)Y'+ // (X⊕Y)'=X XNOR Y
(X⊕Y)⊕Y =XY'+X'YY'+XY+X'Y'Y
(X⊕Y)⊕Y =XY'+0+XY+0
(X⊕Y)⊕Y =XY'+XY
(X⊕Y)⊕Y=X

Simple Method : XOR is Associative
(X⊕Y)⊕Y=X⊕(Y⊕Y)
(X⊕Y)⊕Y=X⊕0
(X⊕Y)⊕Y=X
 Question 59
What is the decimal value of the floating-point number C1D00000 (hexadecimal notation)? (Assume 32-bit, single precision floating point IEEE representation)
 A 28 B -15 C -26 D -28
Question 59 Explanation:
Given 32-bit, single precision floating point IEEE representation
Floating Point number in Hexadecimal = C1D00000

C1D00000 = ( 1100 0001 1101 0000 0000 0000 0000 0000 ) in Binary
• In 32-bit, single precision floating point IEEE representation,
• 1st MSB represents Sign of mantissa : ( 0 = positive value of mantissa and 1 = negative value mantissa  )
• Next 8 bits are for Exponent value
• Last 23 bits represents Mantissa.

So , S =1bit , Exponent= 8 bits , Mantissa = 23 bits.
First bit = sign bit = 1, so number is negative
• Exponent value =131−127 = 4 (127 is the bias in IEEE representation).
• Mantissa = -1.101000000...0
• Floating point number = -1.10100...0000
• Now Convert to decimal  = (1)20+(1)2−1+(0)2−2+(1)2−3 =1+1/2+0+1/8=13/8

Hence we finally get( sign * 2exponent * mantissa) = -26
 Question 60
In Boolean algebra, rule (X+Y)(X+Z) =
 A Y+XZ B X+YZ C XY+Z D XZ+Y
Question 60 Explanation:
(X+Y)(X+Z)
XX +XZ +YX +YZ
X+X+XY+YZ   //(X*X=X)
X+XY+YZ  //X+X=X
X(1+1.Y)  + YZ    // TAKING X AS COMMON
X(1+Y)  + YZ   // 1.Y =Y
X  + YZ   // 1+Y=1
(X+Y)(X+Z) =X+YZ
 Question 61
In an RS flip-flop, if the S line (Set line) is set high (1) and the R line (Reset line) is set low (0), then the state of the flip-flop is
 A Set to 1 B Set to 0 C No change in state D Forbidden
Question 61 Explanation:
When the Set line is set high and the Reset line is set low, then the RS flipflop has the state set to 1. Question 62
 A X. Y + X’ Y’ B X. Y + X. Y C X. Y D X + Y
Question 62 Explanation: Question 63
Number of chips (128 x 8 RAM) needed to provide a memory capacity of 2048 bytes
 A 2 B 4 C 8 D 16
Question 63 Explanation:
Since 8 bits = 1 byte
Each RAM chip has 128 x 8 = 1024 bits
2048 Bytes = 2048 x 8 bits = 16384 bits
Method 1 :
Number of 128 x 8 chips  = Required Total Memory (16384)/1024 = 16
Method 2 :
Number of 128 x 8 chips = Required Total Memory (2048)/128 = 16
 Question 64
The hamming distance between the octets of 0xAA and 0x55 is
 A 7 B 5 C 8 D 6
Question 64 Explanation:
The Hamming Distance between the two codeword: XOR between 2 valid codeword will give another valid codeword, The number of 1's in the valid codeword will indicate hamming distance(d).

OxAA= (1010 1010)2
Ox55 = (0101 0101)2
-----------------------
XOR = (1111 1111)2

Number of 1's in (1111 1111)=8
∴Hamming distance = 8
Note : All the bits of both the words are different with respect to each other, so, the Hamming Distance is equal 8.
 Question 65
The binary equivalent of the decimal number 42.75 is
 A 101010 B 100110 C 101010 D 100110
Question 65 Explanation:
(42.75)10 = (?)2

42 you can convert directly from decimal to binary
(42)10 =( 101010 )2

Now convert Fractional part into binary
Multiply Fractional part with 2 until  fractional part becomes zero
.75
.75 * 2 =1.5  // Fractional part is .5 != 0
.5 * 2 = 1.0  // Fractional part is .0 == 0 So now stop

Now append all this MSBs(for 1.5=1, 1.0=1) to Binary Number
(42.75)10 = (101010.11)2
 Question 66
When two BCD numbers 0x14 and 0x08 are added what is the binary representation of the resultant number?
 A 0x22 B 0x1c C 0x16 D Results in overflow
Question 66 Explanation:
In case of BCD the binary number formed by four binary digits, will be the equivalent code for the given decimal digits. In BCD we can use the binary number from 0000-1001 only, which are the decimal equivalent from 0-9 respectively. Suppose if a number have single decimal digit then it’s equivalent Binary Coded Decimal will be the respective four binary digits of that decimal number and if the number contains two decimal digits then it’s equivalent BCD will be the respective eight binary of the given decimal number. Four for the first decimal digit and next four for the second decimal digit. It may be cleared from an example.

Let, (12)10 be the decimal number whose equivalent Binary coded decimal will be 00010010. Four bits from L.S.B is binary equivalent of 2 and next four is the binary equivalent of 1. Question 67
The number 1102 in base 3 is equivalent to 123 in which base system?
 A 4 B 5 C 6 D 8
Question 67 Explanation:
Let us consider the base be x
(1102)3 = (123)x
(1102)3=1⨉33+1⨉32+2=38
(123)x=1⨉x2+2x+3
Therefore, 38 = 1⨉x2+2x+3
x=5
 Question 68
Any set of boolean operators that is sufficient to represent all boolean expressions is said to be complete. Which of the following is not complete?
 A {NOT, OR} B {NOR} C {AND, OR} D {AND, NOT}
Question 68 Explanation:
• NOR and NAND are the universal gates
• Any logic gate can be implemented by using these NOR and NAND logic gates.
• NOR and NAND are Functionally Complete
Option(C) : {AND, OR}
These two gates do not make a universal gate they are just Basic gates.

Option(D) : {AND, NOT} = NAND = Functionally Complete
Combining these two gates we can make NAND gate which is again a universal gate.

Option(A) : {NOT, OR}} = NOR = Functionally Complete
Combining these two gates we can make NOR gate which is again a universal gate.

Option(B) : NOR = Functionally Complete
NOR is a universal gate.

So we can conclude that Option(C) is Correct Answer
 Question 69
How many programmable fuses are required in a PLA which takes 16 inputs and gives 8 outputs? It has to use 8 OR gates and 32 AND gates.
 A 1032 B 776 C 1284 D 1536
Question 69 Explanation:
• A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND Gates for N input variables, and for M outputs from PLA, there should be M OR Gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms.
• PLAs differ from Programmable Array Logic devices (PALs and GALs) in that both the AND and OR gate planes are programmable.
• Fuses are attached to and- or gate inputs to allow inputs to reach the and - or gates and If fuses don't work , then no input can reach to these gates of PLA • Total programmable fuses= fuses required by AND gates + fuses required by OR gates
• Fuses required by AND gates = 2* no. Of inputs * no. Of and gates = 2*16*32= 1024 fuses
• Fuses required by OR gates = no. Of outputs * no. Of and gates = 8* 32 = 256 ( total outputs should be equal to no. Of OR gates and inputs have to cross AND gates and then goto OR gates)
• Total fuses = 1024+ 256= 1280
 Question 70
In a three stage counter, using RS flip flops what will be the value of the counter after giving 9 pulses to its input? Assume that the value of counter before giving any pulses is 1.
 A 1 B 2 C 9 D 10
Question 70 Explanation:
Three stage counter with RS Flip Flop is 3 bit counter, so after every 8 clock pulse, it will return to initial state. and in the 9th pulse, the counter stage will exceed by 1
Initial  value of the counter  is 1,
state after 8 clock pulse  counter will be again 1,
So, after 9th clock counter will be again 2
 Question 71
The most simplified form of the boolean function, X(A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15) (expressed in sum of minterms) is?
 A A + A’BCD B AB + CD C A + BCD D ABC + D
Question 71 Explanation:
X(A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15) By solving the above K-Map we get X= A+BCD
 Question 72
Two eight bit bytes 1100 0011 and 0100 1100 are added. What are the values of the overflow, carry and zero flags respectively, if the arithmetic unit of the CPU uses 2’s complement form?
 A 0, 1,1 B 1, 1,0 C 1, 0,1 D 0, 1,0
Question 72 Explanation:
1100 0011
+0100 1100
---------------
10000 1111

Carry in and Carry out of MSB is same, so, There is no overflow.
For overflow  we have condition of C = ( Carryout Carry In )
so, Overflow flag = 0,
Carry Flag = 1
Zero Flag = 0
Option (D) is correct
 Question 73
In the standard IEEE 754 single precision floating point representation, there is 1 bit for sign, 23 bits for fraction and 8 bits for exponent. What is the precision in terms of the number of decimal digits?
 A 5 B 6 C 7 D 8
Question 73 Explanation:
IEEE-754 Format  (−1)S1.ME−127
S → sign
M → Mantissa
E → Exponent
Precision can be understood as the maximum accuracy through which a floating point number can be represented.
It is the smallest change that can be represented in floating point representation. The fractional part of a single precision normalized number has exactly 23 bits of resolution, (24 bits with the implied bit).
Precision is represented by ' 1.M ' where M is 23 bits and in total 24 bits are used for representing a précised number .
With 24 bits we can represent  224 numbers (0−224−1). What is that value in decimal ?
Largest number that can be represented in any base x is xnumber of digits−1 (starting from 0).
base Xnumber of digits = base Ynumber of digits
base Xnumber of digits = base Ynumber of digits
Binary represented in base 2 and Decimal represented in base 10
So, 224=10x
Apply log on both sides, then we get
log2224 = log210x
24=xlog210
x=7.22
 Question 74
 A A’C + BC ‘ + CD B ABC + C’D C AB + BC’ + BD’ D AB’ + AC’ + C’D
Question 74 Explanation: Question 75
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits ?
 A 13 B 15 C 16 D 17
Question 75 Explanation:
Given
Ram chip size = 8K x 4 bits = 23 x 210 x 22 = 215 bits
it is given that Bye addressable (215/8 Byte) = 212 bytes
In Array there are 6*4 =24 chip so to address them we need 5 bit .
So, total number of bits required = 12 + 5 = 17 bits
 Question 76
Consider the following sequential circuit What are the values of Q0 and Q1 after 4 clock cycles if the initial values are ?
 A 11 B 01 C 10 D 00
Question 76 Explanation: Q1Q values are 11,10,01,00
• after 1 = 11
• after 2 = 10
• after 3 = 01
• after 4 = 00
 Question 77
Suppose you want to build a memory with 4-byte words with a capacity of 221 bits.
What is the type of decoder required if the memory is built using 2K x 8 RAM chips?
 A 5 to 32 B 6 to 64 C 4 to 64 D 7 to 128
Question 77 Explanation:
Capacity of memory = 221 bit
So, Capacity of memory in Byte will be = 221/23 = 218 bytes
Given Word size of 4 Byte is
So, number of 4-byte words memory should have = 218/ 22 = 216 words
RAM chips size = 2K x 8 (means 8 bit word can be store in one cell of RAM),
therefore, RAM capacity = 211 words.
Number of decoder line required = 216/211 = 25 = 32
5 to 32 Decoder will be required to select the desired row.
 Question 78
Consider the logic circuit given below. The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?
 A 5 B 11 C 16 D 17
Question 78 Explanation:
• Output of AND Gate will available at the input of Ex-OR gate after (Inverter Time + And Gate) = 6 + 10 = 16 ns
• OR gate will reach to the XOR gate in only 11 ns
• 11ns < 16ns, So the output of OR gate will immediately comes at XOR
• which will cause a glitch to happen for 5 n.
• it Means 16 - 11 = 5 ns more will be required the get the actual output
 Question 79
Which of the following is not valid Boolean algebra rule?
 A X.X = X B (X + Y).X = X C X̄ + XY = Y D (X + Y).(X + Z) = X + YZ
Question 79 Explanation:
Option (A)
X.X = X  // 1*1=1 or 0*0=0

Option (B)
(X + Y).X
X.X + X.Y
X + X.Y  // X.X=X
X(1 + Y)
X * 1       // 1+anything =1
X      // 1*anything =anything

Option (C)
X' + XY
(X' + X)(X' + Y)
(1)(X' + Y)  // 1*x=x
(X' + Y)

Option (D)
(X + Y).(X + Z)
X.X + X.Z + X.Y + Y.Z
X(1 + Z + Y) + Y.Z
X + Y.Z
 Question 80
How many different BCD numbers can be stored in 12 switches? (Assume two position or on-off switches)
 A 212 B 212-1 C 1012 D 103
Question 80 Explanation:
• A switch can store only 1 bit  Either  (0 =OFF)  or (=ON)
• It is given that there are 12 switches therefore we have 12 bits
• In Binary Coded Decimal (BCD) Each of the decimal numbers (0-9) is represented by its equivalent binary pattern which is generally of 4-bits.
• It means Each digit of BCD representation takes 4 bits,
• So There will be 12/4 = 3 BCD digits each containing 4 bits
• In Each group maximum 10 numbers can be stored  because A BCD digit can be from 0-9
• So, Different possible BCD numbers in 12 switches are = 10 * 10 * 10 = 1000 = 103
• It means 103 BCD numbers can be stored in this 12 Switches
 Question 81
Perform the following operation for the binary equivalent of the decimal numbers
(-14)10 + (-15)10
The solution in 8 bit representation is :
 A 11100011 B 00011101 C 10011101 D 11110011
Question 81 Explanation:
We need to perform add operation (−14)10+(−15)10

(−14)10
+(−15)10
----------------
=(-29)10
-----------------

So, Results which is Negative Number

Representing Negative Number(-29) in 2's complement
Step 1  : Get 1's complement of 29
Step 2 : add 1 to the result

8-Bit Binary representation of 29 = 00011101
1's complement of 29 = 11100010
Now add 1 to it then we get 11100011
 Question 82
Simplify the following using K-map :
F (A, B, C, D) = Σ (0, 1, 2, 8, 9, 12, 13)
d (A, B, C, D) = Σ (10, 11, 14, 15)
d stands for don’t care condition.
 A A+B'D'+BC B A+B'D'+B'C' C A'+B'C' D A'+B'C'+B'D'
Question 82 Explanation:
F (A, B, C, D) = Σ (0, 1, 2, 8, 9, 12, 13)
d (A, B, C, D) = Σ (10, 11, 14, 15) By solving the above k-map we get A+B'D'+B'C'
 Question 83
___ number of gates are required to implement the boolean function (AB+C) with using only 2 input NOR gates.
 A 2 B 3 C 4 D 5
Question 83 Explanation:
AB+C
= (A+C)(B+C)   //  identity X+YZ=(X+Y)(X+Z)
Now using De-Morgan’s theorem, we have
= (A+C)(B+C)
=(  (  (A+C)(B+C)  )’ )'
= (  (A+C)’ + (B+C)’   )’
So the minimum number of NOR gates required will be 3 Question 84
(A+C’)(B’+C’) simplifies to ______
 A AC’ +B’ B C(A’+B’) C BC’+A D AB’+C’
Question 84 Explanation:
(A+C’)(B’+C’) = AB’+C’

Distributive Law – This law permits the multiplying or factoring out of an expression.
• A(B + C) = A.B + A.C (OR Distributive Law)
• A + (B.C) = (A + B).(A + C) (AND Distributive Law)
 Question 85
The hexadecimal representation of (632)8 is:
 A 19A B 198 C 29A D 291
Question 85 Explanation:
(632)8 = (19A)16

Step 1: Look up each octal digit to obtain the equivalent group of three binary digits
(6)8 = (110)2
(3)8 = (011)2
(2)8 = (010)2

Step 2: Group each value of step 1 to make a binary number.
110 011 010
(632)8 = (110011010)2

Step 3: Now convert the binary number from step 2 to hexa by grouping all the digits of the binary in sets of four starting from the LSB (far right).
0001 1001 1010
Note: add zeros to the left of the last digit if there aren't enough digits to make a set of four.

Step 4: Convert each group of four to the corresponding hexadecimal
0001=1, 1001=9, 1010=A.
So, the octal 632 is equivalent to 19A in hexadecimal.
 Question 86
 A X ↔ y B X ⋀ y C X V y D X → y
Question 86 Explanation:
The given function is nothing but an EXNOR which is same as BICONDITIONAL.
[⨀≡⇔] Question 87
 A 3,2 B 9,4 C 6,5 D 5,2
Question 87 Explanation:
2. In BCD Each digit is represented in 4bit Binary code
3. If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.
4. If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the sum is invalid.
5. To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this addition, add it to the next higher-order BCD digit. ---> for this 1 half adder and  2 full adders
Thus to implement BCD Adder Circuit we require :
• Logic circuit to detect sum greater than 9 and
• One more 4-bit adder(1 half adder and  2 full adders) to add 01102 in the sum if sum is greater than 9 or carry is 1
 Question 88
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 32K x8 RAM from 1K x8 RAM is:
 A 4 B 5 C 6 D 7
Question 88 Explanation:
5
 Question 89
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 32K x8 RAM from 1K x8 RAM is:
 A 4 B 5 C 6 D 7
Question 89 Explanation:
5
 Question 90
 A Ex-OR B NAND gate C OR gate D AND gate
Question 90 Explanation:

First, we can design an AND gate. We can invert it later.

How do we get an AND gate from NOR gates? We can see that (A’ + B’)’ is same as (A.B) , where + represents OR, . represents AND and ' represents complement operation. This is a De Morgan’s law.

We can get the operation of ORing two variables and complementing the result by using a NOR gate. We can also achieve the inverting operating using a NOR gate, just by fusing the two input pins. Question 91
How many inputs are required in full adder circuit?
 A 2 B 3 C More than two inputs D None of the above
Question 91 Explanation:
• The difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two outputs.
• • The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.
 Question 92
What will be the final output of D flip-Flop if the input string is 0010011100?
 A 1 B 0 C Don't care D None of the above
Question 92 Explanation: In D-flip-flop output is same as input given to the flip-flop. So final output would be 0.
In this question LSB,MSB are 0 so final output will be 0,
Note : Here we don't know about order of input
 Question 93
 A AB' + B'CD' + A'B'C' B AB' + A'B'D' + A'B'C' C B'D' + AB' + B'C' D B'D' + A'B'C' + AB'
Question 93 Explanation: Question 94
How many flip-flop are needed to divide the input frequency by 64?
 A 4 B 5 C 6 D 8
Question 94 Explanation:
(26) = 64
So, In order to divide the frequency we need 6 flip flops
 Question 95
The range of the numbers which can be stored in an eight bit register is
 A -128 to +127 B -128 to +128 C -999999 + +999999 D None of these
Question 95 Explanation:
• With n bit numbers possible is = 2n
• Here given n=8 therefore number possible is 28 = 256
• An 8-bit register can store a Unsigned number between 0 and 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 or 28 − 1, that is, 255
• An 8-bit register can store a  signed number range would be -128 to 127 (0 has two representation)
 Question 96
The excess 3 code is also called
 A Cyclomatic redundancy code B Weighted code C Self complementing code D Algebraic code
Question 96 Explanation:
The excess-3 code (or XS3) is a non-weighted code used to express decimal numbers. It is a self-complementary binary coded decimal (BCD) code and numerical system which has biased representation

Excess-3 codes are unweighted and can be obtained by adding 3 to each decimal digit then it can be represented by using 4 bit binary number for each digit. An Excess-3 equivalent of a given binary binary number is obtained using the following steps:
• Find the decimal equivalent of the given binary number.
• Add +3 to each digit of decimal number.
• Convert the newly obtained decimal number back to binary number to get required excess-3 equivalent.
 Question 97
Odd parity of word can be conveniently tested by
 A OR gate B AND gate C NOR gate D XOR gate
Question 97 Explanation:
Odd parity of word can be conveniently tested by XOR gate, since, XOR outputs 1 only when the input has odd number of 1’s.
• The XOR, XNOR, Even Parity, and Odd Parity gates each compute the respective function of the inputs, and emit the result on the output. The two-input truth table for the gates is the following.
• • As you can see, the Odd Parity gate and the XOR gate behave identically with two inputs; similarly, the even parity gate and the XNOR gate behave identically. But if there are more than two specified inputs,
• the XOR gate will emit 1 only when there is exactly one 1 input, whereas the Odd Parity gate will emit 1 if there are an odd number of 1 inputs.
• The XNOR gate will emit 1 only when there is not exactly one 1 input, while the Even Parity gate will emit 1 if there are an even number of 1 inputs.
 Question 98
If the input J is Connected through K input of J-K, then flip-flop will behave as a
 A D type flip-flop B T type flip-flop C S-R flip flop D Toggle switch
Question 98 Explanation:
• If J and K are both low then no change occurs.
• If J and K are both high at the clock edge then the output will toggle from one state to the other.
• It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states.
• It can also act as a T flip-flop to accomplish toggling action if J and K are tied together.
• This toggle application finds extensive use in binary counters
 Question 99
To build a mod-19 counter the number of flip-flop required is
 A 3 B 5 C 7 D 8
Question 99 Explanation:
Number of flip-flops required to construct a binary modulo N counter is
2x = N
Where x= ceiling (log2N)
Given Question we have to construct mod 19
therefore 2x = 19
x=ceiling (log219)
x=4.something
x=5
 Question 100
​ If a clock with time period "T" is used with n stage shift register, then output of final stage will be delayed by
 A NT sec B (n-1)T sec C N/Tsec D (2n-1)T sec
Question 100 Explanation:
• Shift Register is a group of flip flops used to store multiple bits of data.
• The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses.
• An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.
• The registers which will shift the bits to left are called “Shift left registers”.
• The registers which will shift the bits to right are called “Shift right registers"
• After Each shift next significant bit moves to LSB and the bit in LSB is read in right shift operation.
• After Each shift next significant bit moves to MSB and the bit in MSB is read in Left shift operation.
• so finally  The last element moves to LSB position after (n-1) shifts i.e, T(n-1) seconds
 Question 101
​ A sequential circuit outputs a ONE when an even number (>0) of one's are input; Otherwise the output is ZERO. The minimum number of states required is
 A 0 B 1 C 2 D 3
Question 101 Explanation: Question 102

In computers, subtraction is generally carried out by

 A 1’s complement B 10’s complement C 2’s complement D 9’s complement
Question 102 Explanation:
In computers, subtraction is generally carried out by 2’s complement
With the help of subtraction by 2’s complement method we can easily subtract two binary numbers.

The operation is carried out by means of the following steps:
(i) At first, 2’s complement of the subtrahend is found.
(ii) Then it is added to the minuend.
(iii) If the final carry over of the sum is 1, it is dropped and the result is positive.
(iv) If there is no carry over, the two’s complement of the sum will be the result and it is negative.
 Question 103

The boolean expression A'⋅B + A⋅B' + A⋅B is equivalent to

 A A+B B A⋅B C (A+B)' D A'⋅B
Question 103 Explanation:
• A'.B + A.B' + A.B
• A'.B + A.B + A.B'
• B(A' + A) + A.B'  // Taking B as common
• B + A.B'
• (B+A).(B+B') // Distributive Law
• (B+A).1   // (0+1=1) or (1+0=1)
• B+A  // 1.anything=anything
 Question 104
The relation ≤ and > on a boolean algebra are defined as :
```x ≤ y if and only if x ∨ y = y
x < y means x ≤ y but x ≠ y
x ≥ y means y ≤ x and
x > y means y < x```

Consider the above definitions, which of the following is not true in the boolean algebra ?

(i) If x ≤ y and y ≤ z, then x ≤ z
(ii) If x ≤ y and y ≤ x, then x = y
(iii) If x < y and y < z, then x ≤ y
(iv) If x < y and y < z, then x < y

Choose the correct answer from the code given below:

Code:
 A (iv) only B (iii) only C (i) and (ii) only D (ii) and (iii) only
Question 104 Explanation:
only Option(B) is correct Question 105
Consider the following boolean equations :
(i) wx + w(x + y) + x(x + y)= x + wy
(ii) (wx’(y + xz’) + w’x’)y = x’y

What can you say about the above equations ?
 A Both (i) and (ii) are true B (i) is true and (ii) is false C Both (i) and (ii) are false D (i) is false and (ii) is true
Question 105 Explanation:
(i) wx + w(x + y) + x(x + y)= x + wy
wx + w(x+y) +x(x+y)
= wx + wx + wy + x + xy
= wx + wy + x + xy
= x(w+y+1) + wy  // taking x as common
= x+wy   // 1+anything=1

(ii) (wx’(y + xz’) + w’x’)y = x’y
(wx’(y+xz’)+w’x’)y
= wx’y + wx'xz'+ w’x’y
= wx’y + w’x’y  // x'x = 0
= x’y(w+w')
= x’y
 Question 106
Find the boolean expression for the logic circuit shown below :
(1-NAND gate, 2-NOR gate, 3-NOR gate) A AB B AB’ C A’B’ D A’B
Question 106 Explanation: Question 107

Which of the following statements are true ?

(i) Every logic network is equivalent to one using just NAND gates or just NOR gates.
(ii) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(iii) No two Boolean algebras with n atoms are isomorphic.
(iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.

Choose the correct answers from the code given below :

Code :
 A (i) and (iv) only B (i) and (ii) only C (i), (ii) and (iii) only D (ii), (iii) and (iv) only
Question 107 Explanation:
Option(A): Every logic network is equivalent to one using just NAND gates or just NOR gates :  True
NAND gate and NOR gates are universal gates by using these we can construct anything

Option(B):Boolean expressions and logic networks correspond to labelled acyclic digraphs : True
Refer : https://en.wikipedia.org/wiki/Propositional_directed_acyclic_graph

Option(C) and (D) : False
An atom of a Boolean algebra is an element x such that there exist exactly two elements y satisfying y ≤ x, namely x and 0. A Boolean algebra is said to be atomic when every element is a sup of some set of atoms (the bottom element is always the empty sup).

Every finite Boolean algebra is atomic, and moreover isomorphic to the power set 2X of the set X of its atoms, under the operations of union, intersection, and complement, with 0 and 1 realized by respectively the empty set and X. Conversely every finite power set forms a Boolean algebra under union, intersection, and complement
 Question 108
The digital multiplexer is basically a combination logic circuit to perform the operation
 A AND-AND B OR-OR C AND-OR D OR-AND
Question 108 Explanation:
Schematic Diagram of 2 to 1 Multiplexer using Logic Gates
A MUX need AND gates equal to the number of input channels, NOT gates equal to the number of Control signals and a single OR gate. The equation of digital multiplexer is given by
Youtput =D0(S0)'+D1S0
Here firstly we have to solve two AND operations followed by one OR operation
 Question 109
 A OR gate B AND gate C NAND gate D EX-OR gate
Question 109 Explanation:
Given output f = (x + x') + (y + y') = (x + y) + (x' + y')

(x + y) + (x' + y')  is  rewriting the given solution keep in mind that known output will be (x + y)(OR gate)

(x + y) is coming from OR gate
(x'+ y') is output of a gate by using the inputs x and y
This is possible only when the ? marked box is a NAND gate.
 Question 110

In the following gate network which gate is redundant?

 A Gate no.1 B Gate no.2 C Gate no.3 D Gate no.4
Question 110 Explanation:
w' + w'z + z'xy
= w'(1 + z) + z'xy
= w' + z'xy
Gate number 2 which produces w'z is redundant as it has been eliminated in final result
So, option (B) is correct
 Question 111
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent? A NOT B OR C AND D XOR
Question 111 Explanation: Question 112
In comparison with static RAM memory, the dynamic RAM memory has
 A Lower bit density and higher power consumption B Higher bit density and higher power consumption C Lower bit density and lower power consumption D None of the option
Question 112 Explanation:
BASIS FOR COMPARISON SRAM DRAM
Speed Faster Slower
Size Small Large
Cost Expensive Cheap
Used in Cache memory Main memory
Density Less dense Highly dense
Construction Complex and uses transistors and latches. Simple and uses capacitors and very few transistors.
Single block of memory requires 6 transistors Only one transistor.
Charge leakage property Not present Present hence require power refresh circuitry
Power consumption Low High
 Question 113
The nature of any number i.e., positive or negative is recognized by its:
 A MSB B LSB C Bits D Nibble
Question 113 Explanation:
we have 3 elements in a 32-bit floating point representation :
(i) Sign
(ii) Exponent
(iii) Mantissa
Sign bit is the first bit(MSB) of the binary representation. '1' implies negative number and '0' implies positive number.
Exponent is decided by the next 8 bits of binary representation.
Mantissa is calculated from the remaining 23 bits of the binary representation. It consists of '1' and a fractional part
 Question 114
The theory of bubbled input OR gate is interchangeable with a bubbled output AND gate is demonstrated and proved by:
 A Karnaugh map B DeMorgan’s second theorem C The commutative law of addition D The associative law of multiplication
Question 114 Explanation:
According to DeMorgan’s second theorem, a NOR gate is equivalent to a bubbled AND gate.
The Boolean expressions for the bubbled AND gate can be expressed by the equation shown below.
• For NOR gate, the equation is:  Z=(A+B)'
• For the bubbled AND gate the equation is:  Z= (A'.B')
As the NOR and bubbled gates are interchangeable, i.e., both gates have exactly identical outputs for the same set of inputs.
• Therefore, the equation can be written as shown below :  (A+B)'=A'.B'-------(1)
• This equation (1) or identity shown above is known as DeMorgan’s Theorem.
• The symbolic representation of the theorem is shown in the figure below: Question 115
Which IC is used for the implementation of 1 to 16 DEMUX?
 A IC 74154 B IC 74155 C IC 74139 D IC 74138
Question 115 Explanation:
IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

Note:
• There are several types of De-multiplexers based on the output configurations such as 1:4, 1:8 and 1:16.
• These are available in different IC packages and some of the most commonly used de-multiplexer ICs includes 74139 (dual 1:4 DEMUX), 73136 (1:8 DEMUX), 74154 (1:16 DEMUX), 74159 (1:16 DEMUX open collector type), etc.
 Question 116
Which of the following logic expression is incorrect?
 A 1 ⊕ 0=1 B 1 ⊕ 1 ⊕ 0=1 C 1 ⊕ 1 ⊕ 1=1 D 1 ⊕ 1 =0
Question 116 Explanation:
EX-OR  return 1 when inputs are different otherwise 0  i.e, for same input it return 0
(A)1 ⊕ 0 = 1         //  True because different input
(B) 1 ⊕ 1 ⊕ 1 = 1  //  True  1 ⊕ 1 =0 and 0 ⊕ 1 =1
(C) 1 ⊕ 1 ⊕ 0 = 1  // False  1 ⊕ 1 =0 and 0 ⊕ 0 =0
(D) 1 ⊕ 1 = 0      // True  because Same  input
 Question 117
In which of the following adder circuits, the carry look ripple delay is eliminated?
Question 117 Explanation:
• Each full adder has to wait for its carry-in from its previous stage full adder.
• Thus, nth full adder has to wait until all (n-1) full adders have completed their operations.
• This causes a delay and makes ripple carry adder extremely slow.
• The situation becomes worst when the value of n becomes very large.
• It generates the carry-in of each full adder simultaneously without causing any delay.
• The time complexity of carry look ahead adder = Θ (logn).
• The working of carry look ahead adder is based on the principle:The carry-in of any stage full adder is independent of the carry bits generated during intermediate stages.
 Question 118
The output of a sequential circuit depends on
 A Presents inputs only B Past inputs only C Both present and past inputs D Present outputs only
Question 118 Explanation:
• Sequential circuit contains a set of inputs and outputs S .
• The outputs s of sequential circuit depends not only on the combination of present inputs but also on the previous outputs s.
• Previous output is nothing but the present state. Therefore, sequential circuits contain combinational circuits along with memory storage elements.
• Some sequential circuits may not contain combinational circuits, but only memory elements.
 Question 119
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the
 A Clock input of all flip-flops B Clock input of one flip flops C J and K inputs of all flip flops D J and K inputs of one flip-flop
Question 119 Explanation:
• In a ripple counter using edge-triggered JK flip-flops the pulse input is applied to clock input of one flip flop then
• First Flip flop is clocked and the rest are clocked from their previous flip flop's output. above diagram is 3 bit ripple counter using JK flip flop Here you can see in diagram Q0,Q1 applied to clock input of one flip flop
 Question 120
A decimal number has 30 digits. Approximately, how many digits would the binary representation have?
 A 30 B 60 C 90 D 120
Question 120 Explanation:
Maximum 30 digit decimal number = 1030 – 1
Maximum x bit binary number = 2x – 1
1030 – 1 = 2x – 1
Apply log on both then we get
log 21030 = x
x = 30 log 210
x = 30 x 3.3
x = 99
Therefore minimum 99 bits we require  to represent 30 digit number
 Question 121
The result of the subtraction FD​16 - ​8816​ is
 A 75​ 16 B 65 16 C 5E 16 D 10 16
Question 121 Explanation:
FD​16 - ​8816
• FD​16=(253)10
• 8816=(136)10
Therefore (253)10 - (136)10 = (117)10
Now represent (117)10 in Hexadecimal :
(117)10 = (75)16
 Question 122
How many RAM chips of size (256K x 1 bit) are required to build 1M Byte memory?
 A 8 B 10 C 24 D 32
Question 122 Explanation:
We need 1 Mbytes, i.e., 1 x 220 x 8 bits.
We have RAM chips of capacity 256 Kbits = 28 x 210bits.
Total number of RAM chip = Total size /1 RAM size
(220 x 23 bits.)/(28 x 210bits.) =25 = 32
 Question 123
Disadvantage of dynamic RAM over static RAM is
 A Higher power consumptions B Variable speed C Need to refresh the capacitor charge every once in two milliseconds D Higher bit density
Question 123 Explanation:
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, SRAM does not have to be periodically refreshed but DRAM periodically refreshed
BASIS FOR COMPARISON SRAM DRAM
Speed Faster Slower
Size Small Large
Cost Expensive Cheap
Used in Cache memory Main memory
Density Less dense Highly dense
Construction Complex and uses transistors and latches. Simple and uses capacitors and very few transistors.
Single block of memory requires 6 transistors Only one transistor.
Charge leakage property Not present Present hence require power refresh circuitry
Power consumption Low High
 Question 124
Which of the following circuit can be used as parallel to serial converter?
 A Multiplexer B Demultiplexer C Decoder D Digital Counter
 Question 125
The number of full and half adders required to add 16-bit numbers is
Question 125 Explanation:
• IF 16- bit operation then we need 15-FA,1-HA
• IF 17- bit operation then we need 16-FA,1-HA
• In general for n-bit operation : (n-1)FA and 1-HA are required
To add two 16 bit numbers using minimum gates, the least significant bits of both the numbers can be added using a half adder and for remaining 15 bits of both the numbers, full adders can be used. 1 Half Adder and 15 Full Adders will be required.
 Question 126
Which of the following expression is not equivalent to ~x?
 A X NAND x B X NOR x C X NAND 1 D X NOR 1
Question 126 Explanation:
• X NAND x  = (x.x)'= x'
• X NOR x     =(x+x)'= x'x' = x'
• X NAND 1 = (x.1)'=x'+0=x'  // 0+anything=anything
• X NOR 1   = (x+1)'=x'0=0     // 0*anything=0
 Question 127
Which one of the following set of gates are best suited for parity checking and parity generation
 A AND,OR,NOT gates B EX-NOR or EX-OR gates C AND gates D NOR gates
Question 127 Explanation:

### Parity generator and checker

A parity generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a circuit that checks the parity in the receiver is called parity checker
• The sum of the data bits and parity bits can be even or odd .
• In even parity, the added parity bit will make the total number of 1s an even amount
• whereas in odd parity the added parity bit will make the total number of 1s odd amount.
• sum of odd number of 1s is always 1 and sum of even number of 1s is always zero. Such error detecting and
• correction can be implemented by using Ex-OR gates
•  Ex-OR gate produce zero output when there are even number of inputs
Parity generation
• The XNOR gate will emit 1 only when there is not exactly one 1 input.
• This feature can be used for parity generation.
• Suppose A at sender side wants to send 1001. XNOR gate will give parity as 0.
• But if A sends 1000 XNOR gate gives 1 as parity
Parity check
• B computes parity: 1+0+0+1+0 (mod 2) = 0 //this can be achieved by EXOR gate
•  Ex-OR gate produce zero output when there are even number of inputs
• Ex-OR gate produce 1 output when there are odd number of inputs
 Question 128
​ In computers, subtraction is generally carried out by
 A 1’s complement B 10’s complement C 2’s complement D 9’s complement
Question 128 Explanation:
In computers, subtraction is generally carried out by 2’s complement
With the help of subtraction by 2’s complement method we can easily subtract two binary numbers.

The operation is carried out by means of the following steps:
(i) At first, 2’s complement of the subtrahend is found.
(ii) Then it is added to the minuend.
(iii) If the final carry over of the sum is 1, it is dropped and the result is positive.
(iv) If there is no carry over, the two’s complement of the sum will be the result and it is negative.
 Question 129
​ The boolean expression A’⋅B+A.B’+A.B is equivalent to
 A A+B B A.B C (A+B)’ D A’.B
Question 129 Explanation:
•  A’⋅B+A.B’+A.B
•  A’⋅B+A(B’+B) // taking A as common
•  A’⋅B+A(1)
•  A +A’⋅B
• (A +A’)(A +B)
• A+B  //  A +A’=1
 Question 130
The relation​ ​ ≤ and > on a boolean algebra are defined as :
• x ≤ y and only if x ∨ y = y
• x < y means x ≤ y but x ≠ y
• x ≥ y means y ≤ x and
• x > y means y < x
Consider the above definitions, which of the following is not true in the boolean algebra ?

(i) If x ≤ y and y ≤ z, then x ≤ z
(ii) If x ≤ y and y ≤ x, then x=y
(iii) If x < y and y < z, then x ≤ y
(iv) If x < y and y < z, then x < y
 A (iv) only B (iii) only C (i) and (ii) only D (ii) and (iii) only
Question 130 Explanation:
only Option(B) is correct Question 131
Consider the following boolean equations :
(i) wx + w(x + y) + x(x + y)= x + wy
(ii) (wx’(y + xz’) + w’x’)y = x’y

What can you say about the above equations ?
 A Both (i) and (ii) are true B (i) is true and (ii) is false C Both (i) and (ii) are false D (i) is false and (ii) is true
Question 131 Explanation:
(i) wx + w(x + y) + x(x + y)= x + wy
wx + w(x+y) +x(x+y)
= wx + wx + wy + x + xy
= wx + wy + x + xy
= x(w+y+1) + wy  // taking x as common
= x+wy   // 1+anything=1

(ii) (wx’(y + xz’) + w’x’)y = x’y
(wx’(y+xz’)+w’x’)y
= wx’y + wx'xz'+ w’x’y
= wx’y + w’x’y  // x'x = 0
= x’y(w+w')
= x’y
 Question 132
Find the boolean expression for the logic circuit shown below :
(1-NAND gate, 2-NOR gate, 3-NOR gate) A AB B AB’ C A’B’ D A’B
Question 132 Explanation: Question 133
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is
 A 0xC2206000 B 0xC2006666 C 0xC2006000 D 0xC2206666
Question 133 Explanation:  Bias = 2N−1 −1
N−Number of bits to represent exponent in binary

Given -40.1
(40)10 = (101000)2

For converting Fractional part into binary form just multiply with 2 until it get the same number
• 0.1 * 2 =0.2  - 0
• 0.2 * 2 =0.4  - 0
• 0.4 * 2 =0.8  - 0
• 0.8 * 2 =1.6   - 1
• 0.6 * 2 =1.2   - 1
• 0.2 * 2 =0.4  - 1 // stop coz 0.2*2 we already did it is repeating
(0.1)10 =0.00011

(40.1)10 = 101000.00011 =  1.0100000011 * 25
• Biased exponent = actual + bias = 5+bias
• where bias=28−1−1=127
• Biased exponent = 5+127=132 = (1000 0100)2
• sign = 1
• Mantisa = 010100000011 ....00
Therefore, number represented as 1  1000 0100  010100000011 ....00

on converting to hexadecimal we get (0xC2206666)16
 Question 134
​Which of the following statements are true ?
(i) Every logic network is equivalent to one using just NAND gates or just NOR gates.
(ii) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(iii) No two Boolean algebras with n atoms are isomorphic.
(iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.
 A (i) and (iv) only B (i) and (ii) only C (i), (ii) and (iii) only D (ii), (iii) and (iv) only
Question 134 Explanation:
Option(A): Every logic network is equivalent to one using just NAND gates or just NOR gates :  True
NAND gate and NOR gates are universal gates by using these we can construct anything

Option(B):Boolean expressions and logic networks correspond to labelled acyclic digraphs : True

Option(C) and (D) : False
An atom of a Boolean algebra is an element x such that there exist exactly two elements y satisfying y ≤ x, namely x and 0. A Boolean algebra is said to be atomic when every element is a sup of some set of atoms (the bottom element is always the empty sup).

Every finite Boolean algebra is atomic, and moreover isomorphic to the power set 2X of the set X of its atoms, under the operations of union, intersection, and complement, with 0 and 1 realized by respectively the empty set and X. Conversely every finite power set forms a Boolean algebra under union, intersection, and complement
 Question 135
 A Ex-Or B NAND gate C OR gate D AND gate
Question 135 Explanation:

First, we can design an AND gate. We can invert it later.

How do we get an AND gate from NOR gates? We can see that (A’ + B’)’ is same as (A.B) , where + represents OR, . represents AND and ' represents complement operation. This is a De Morgan’s law.

We can get the operation of ORing two variables and complementing the result by using a NOR gate. We can also achieve the inverting operating using a NOR gate, just by fusing the two input pins. Question 136
A sinusoidal signal is analog signal, because:
 A It can have a number of values between the negative and positive peaks B It is negative for one half cycle C It is positive for one half cycle D It has positive as well as negative values
Question 136 Explanation:
• A sinusoidal wave is an analog signal.
• Analog signal is a continuous signal and digital signal is a discrete signal
• An analog electrical signal is a signal with infinite number of amplitudes in the range of values of independent variable.
• Analog signals can take on any value in the continuous interval.
• A sinusoidal signal is a continuous signal with respect to time.
 Question 137
What will be the Excess-3 code for 1001?
 A 1001 B 1010 C 1011 D 1100
Question 137 Explanation:
• Decimal = 9
• 1001 = 9 in Decimal
• So add 3 to it 9+3=12
• Excess-3 Code  for 1001  = 1100
 Question 138
What will be the final output of D flip-flop, if the input string is 11010011?
 A 1 B 0 C Don't Care D None of Above
Question 138 Explanation: In D-flip-flop output is same as input given to the flip-flop. So final output would be 0.
In this question LSB,MSB are 1 so final output will be 1,
Note : Here we don't know about order of input
 Question 139
 A AB' + B'CD' + A'B'C' B AB' + A'B'D' + A'B'C' C B'D' + AB' + B'C' D B'D' + A'B'C' + AB'
Question 139 Explanation: Question 140
The Decimal equivalent of the Hexadecimal number (A09D)16 is
 A 31845 B 41117 C 41052 D 32546
Question 140 Explanation:
A09D16 = 10∙163+0∙162+9∙161+13∙160 = 40960+0+144+13 = 4111710
 Question 141
Which one of the following is true?
 A NAND gate and AND gate both are universal gates B NOR gate and OR gate both are universal gates C NAND gate and OR gate both are universal gates D NAND gate and NOR gate both are universal gates
Question 141 Explanation:
• NAND and NOR are called universal gates because all the other gates like and,or,not,xor and xnor can be derived from it.
• Nand actually means NOT of AND,so NAND is a combination of AND and NOT.A NAND gate can also be implemented using inverted OR inputs and that's why also called as bubbled OR gate.
• Similarly NOR means NOT of OR,so it is a combination of OR and a NOT gate. A NOR gate is also implemented using inverted AND inputs and so also called as bubbled AND gate.
 Question 142
Which one of the following is the function of a multiplexer
 A To decode information B To select 1 out of N input data sources and to transmit it to single channel C To transmit data on N lines D To perform serial to parallel conversion
Question 142 Explanation:
• A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines
• It is a combinational circuit which have many data inputs and single output depending on control or select inputs.​
• For N input lines, log n (base2) selection lines, or we can say that for 2n input lines, n selection lines are required.
 Question 143
​ In digital logic, if A ​ ⊕ ​ B=C, then which one of the following is true?
 A A ​ ⊕ ​ C=B B B ​ ⊕ ​ C=A C A ​ ⊕ ​ B ​ ⊕ ​ C=0 D Both A) and B) E None
Question 143 Explanation:
Given A⊕B=C

Truth Table of E-OR
• A⊕0=A
• A⊕1=A'
• A⊕A'=1
• A⊕A=0

A⊕C
≡A⊕(A⊕B)   // C=A⊕B
≡(A⊕A)⊕B
≡0⊕B≡B

B⊕C
≡B⊕(A⊕B)
≡B⊕(B⊕A)
≡(B⊕B)⊕A
≡0⊕A
≡A

A⊕B⊕C
≡A⊕B⊕(A⊕B)
≡A⊕B⊕(B⊕A)
≡A⊕(B⊕B)⊕A
≡A⊕0⊕A
≡A⊕A
≡0

All are TRUE
 Question 144
Which of the given number has its IEEE-754 32 bit floating point representation as
10000000 110 0000 0000 0000 0000 0000
 A 2.5 B 3 C 3.5 D 4.5
Question 144 Explanation:
IEEE-754 32 bit floating point representation has excess-128 notation and first MSB represents sign bit for mantissa, next 8 bits represents the exponent(excess 127) and last 23 bits represent the value of mantissa.
Given data,
Floating point = 0 10000000 110 0000 0000 0000 0000 0000
Sign = 0
0 at MSB represents that mantissa is positive.
Next 8 bits, i.e. 10000000 = exponent = 2128 but as it is excess 127 notation,
so actual value of exponent = 2128 – 127 = 21
Value of mantissa in normalized form = 1.110 0000 0000 0000 0000 0000
Value=(-1)s *(1.110000.......) * 21
Value  =(-1)0 ⨉(1⨉20+ 1⨉2-1 + 1⨉ 2-2 + 0⨉2-3+........)⨉21 =3.5
 Question 145
The range of integers that can be represented by an n bit 2’s complement number system is:
 A – 2n – 1 to 2n – 1 – 1 B – (2n – 1 – 1) to (2n – 1 – 1) C – 2n – 1 to 2n – 1 D – (2n – 1 + 1) to (2n – 1 – 1)
Question 145 Explanation:

For n bit 2’s complement numbers, range of number is -(2(n-1)) to +(2(n-1)-1)
• Number of distinct numbers that can be represented using n bits = 2n
• In Unsigned numbers these corresponds to numbers from 0 to 2n−1.
• In Signed numbers in 1′s complement or sign magnitude representation, these corresponds to numbers from −(2n−1−1) to ( 2n−1 −1 )   with 2 separate representations for 0.)
• In Signed numbers in 2′s complement representation, these corresponds to numbers from (−2n−1 ) to (2n−1 −1 )   with a single representation for 0.
 Question 146
How many 32K X 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
 A 8 B 32 C 64 D 128
Question 146 Explanation:
To Design RAM we require = 256K * 8
Total Number of RAM Chips = [256∗K∗8]/[32∗K∗1]=64
SO, IT REQUIRES 8 PARALLEL LINES AND IN EACH PARALLEL LINE 8 SERIAL RAM CHIP ARE REQUIRED
 Question 147
A modulus -12 ring counter requires a minimum of
 A 10 flip-flops B 12 flip-flops C 8 flip-flops D 6 flip-flops
Question 147 Explanation:
• The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number.
• A “mod-n” ring counter will require “n” number of flip-flops connected together to circulate a single data bit providing “n” different output states.
• for mod 12 we require “12” number of flip-flops
 Question 148
The complement of the Boolean expression AB ( B’C + AC ) is
 A ( A’ + B’ ) + ( B + C’ )( A’ + C’ ) B ( A’ + B’ ) + ( BC’ + A’C’ ) C ( A’ + B’ )( B + C’) + ( A + C’ ) D ( A + B )( B’ + C )( A + C )
Question 148 Explanation:
AB(B'C + AC)
[AB(B'C + AC)]'    // Complementing
(AB)' + (B'C + AC)'   // Demorgan's law
(AB)' + (B'C)' (AC)'
(A' + B') + ((B')'+C') (A'+C')
(A' + B') + (B+C') (A'+C')  // Demorgan's law
 Question 149
The code which uses 7 bits to represent a character is
 A ASCII B BCD C EBCDIC D Gray
Question 149 Explanation:

The American Standard Code for Information Interchange
ASCII is a computer code which uses 128 different encoding combinations of a group of seven bits (27 = 128) to represent,(Extended ASCII uses 8 bits)
• characters A to Z, both upper and lower case
• special characters, < . ? : etc
• numbers 0 to 9
• special control codes used for device control
1. ASCII uses 7 bits to represent a character
2. Binary coded decimal (BCD) is a system of writing numerals that assigns a four-digit binary code to each digit 0 through 9 in a decimal (base-10) numeral.
3. Extended Binary Coded Decimal Interchange Code (EBCDIC) is an eight-bit character encoding.
4. The reflected binary code (RBC), also known as Gray code , is a binary numeral system where two successive values differ in only one bit (binary digit).
 Question 150
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
 A 0, 17 B 16, 1 C 1, 16 D 8, 8
Question 150 Explanation:
• IF 16- bit operation then we need 15-FA,1-HA
• IF 17- bit operation then we need 16-FA,1-HA
• In general for n-bit operation : (n-1)FA and 1-HA are required
To add two 17 bit numbers using minimum gates, the least significant bits of both the numbers can be added using a half adder and for remaining 16 bits of both the numbers, full adders can be used. 1 Half Adder and 16 Full Adders will be required.
 Question 151
Minimum number of 2x1 multiplexers required to realize the following function,
f = A’B’C + A’B’C’
Assume that inputs are available only in true form and Boolean constant 1 and 0 are available.
 A 1 B 2 C 3 D 7
Question 151 Explanation:
A'B'C + A'B'C'
A'B'( C + C' )  // taking A'B' as common
A'B' (1)    // C + C'=1
A'B'     // 1*anything = anything Question 152
The number of 1’s in the binary representation of (3*4096 + 15*256 + 5*16 + 3) are:
 A 8 B 9 C 10 D 12
Question 152 Explanation:
3*4096 + 15*256 + 5*16 + 3
= (2 + 1)*4096 + (8 + 4 + 2 + 1)*256 + (4 + 1)*16 + 2 + 1
= (2 + 1)*212 + (23 + 22 + 2 + 1 )*28 + (22 + 1)*24 + 2 + 1
= (213 + 212) + (211 + 210 + 29 + 28) + (26 + 24) + 2 + 1

213  is 1 followed by 12 zeros,
212  is 1 followed by 11 zeros
211  is 1 followed by 10 zeros
'
'
'

adding all these numbers give total 10 1's
 Question 153
The boolean expression AB + AB’+ A’C + AC is independent of the boolean variable
 A A B B C C D None of these
Question 153 Explanation:
AB+AB'+A'C+AC
=A(B+B')+C(A+A')
=A(1)+C(1)    // (B+B')=1 ; A+A'=1
=A+C   // 1*anything =1
As the expression is independent of 'B'
 Question 154
The decimal number has 64 digits.The number of bits needed for its equivalent binary representation is?
 A 200 B 213 C 246 D 277
Question 154 Explanation:
Maximum 64 digit decimal number = 1064 – 1
Maximum x bit binary number = 2x – 1
1064 – 1 = 2x – 1
1064  = 2x
Apply log on both sides then we get
log 21064 = log 22x
log 21064 = x log 22
log 21064 = x
x = 64 log 210
x = 64 x 3.322
x = 212.6 (approximately 213)

Minimum 213 bits are required to 64 digit number
 Question 155
Which of the following Boolean equations is/are correct?
X(X'+ Y) = XY'
X + XY = X
X + X'Y = X + Y
 A Only (iii) B Only (ii) C Only (i) D Both (ii) and (iii)
Question 155 Explanation:
X(X'+ Y) = XY'
XX'+XY  // USING DISTRIBUTIVE
0+XY   //XX'=0
XY  // 0+anything =anything

X + XY = X
X(1 + Y) // TAKING X AS COMMON
X(1) // 1+ANYTHING=1
X

X + X'Y = X + Y
(X+X') (X+Y)
1*(X+Y)
X+Y
 Question 156
The following circuit represents the function of a 2–input __________ logic gate.
 A Exclusive-OR B Exclusive-NOR C NAND D NOR
Question 156 Explanation: Question 157
The maximum number of boolean functions that can be formed using 3 boolean variable is ____.
 A 512 B 256 C 128 D 1024
Question 157 Explanation:
We have n boolean variables
So, we will have total of 2n combination of truth table values
For each of these 2n values, to define a boolean function they may be 0 or 1.
So we have 2 choices each for each 2n combination of truth table values
So, Total number of Boolean functions are  22n

Given n=3
Total number of Boolean functions are  223 =28=256
 Question 158

Which of the following does NOT represent the Exclusive NOR operation over the binary variables A and B?

 A A’ ⊕ B’ B A ⊕ B’ C A’ ⊕ B D AB + A’B’
Question 158 Explanation:
Exclusive-NOR  and Exclusive-OR of A and B is given by the Expressions
• A⊙B = A.B + A'.B' (E-NOR )
• A⊕B = A'.B + A.B' (E-OR )

A'⊕B'
(A')'.B' + A'.(B')'
A.B' + A'.B  which is NOT equivalent to A⊙B.

A⊕B'
A'.B' + A.(B')'
A'.B' + A.B   which is equivalent to A⊙B.

A'⊕B
(A')'.B + A'.B'
A.B + A'.B'  which is equivalent to A⊙B.

A.B + A'.B'
which is equivalent to A⊙B.

Hence A is FALSE.
 Question 159
Suppose x and y are floating point variables that have been assigned the values x = 8.8 and y = 3.5. What will be the value of the following arithmetic expression?
2 * x / 3 * y
 A 20.3333 B 24.4545 C 16.3535 D 20.5333
Question 159 Explanation: x=8.8 and y=3.5
2*x/3*y

( (2*x)/3*y)  // both (*, /)  have  same  priority but associativity will be from left to right

( ((2x) /3 ) * y)
((17.6/3) *y)
(5.866 * 3.5)
20.5333

Note :
Post Fix : (2x * 3 / y *)
2 * 8.8 * 3 / 3.5 *
 Question 160
The boolean function X’Y’ + XY + X’Y, where X’ represents the complement of X, is equivalent to ____
 A X + Y’ B X’ + Y’ C X’ + Y D X + Y
Question 160 Explanation:
• A + A = A
• A + A' = 1
• A. A = A
• A. A' = 0
• (A+BC)= (A+B)(A+C)

Given
xy + x'y'+x'y
= xy+x'(y+y')  //taking x’ common
= xy+x'. 1   // from rule2
= (x + x’)(y+x')  //from rule5
= 1.(x’+y)  //from rule2
xy + x'y'+x'y     =  (x’+y) .
 Question 161

What is the base(radix) of the number system whose numbers 312, 20 and 13.1 satisfy the following equation?

312/20 = 13.1
 A 8 B 4 C 5 D 6
Question 161 Explanation:
Let r  be the base of the number system
Given 312/20 = 13.1
L.H.S = ( 3r2 + 1*r 1+ 2*r0 ) / ( 2r+0*r0)
L.H.S = ( 3r2 + r + 2 ) / ( 2r) = ( 3r / 2 ) + ( 1 / 2 ) + ( 1 / r )
R.H.S = 1*r1 + 3*r0 + ( 1 / r ) = r + 3 + ( 1 / r )
Given L.H.S = R.H.S in the equation
( 3r / 2 ) + ( 1 / 2 ) + ( 1 / r ) = r + 3 + ( 1 / r )
3r + 1 = 2r + 6
3r  = 2r + 5
r = 5
SO BASE will be 5
 Question 162

What is the hexadecimal representation of the decimal number 8537?

 A (2059)16 B (2159)16 C (2195)16 D (2157)16
Question 162 Explanation:
Step 1 : convert the given number into binary number
(8537)10 = (10000101011001)2

Step 2 : Divide the binary number into groups of 4 starting from LSB(right) if it is integer part and start from left for fraction part.
(10 0001 0101 1001)2

Step 3 : Convert each group of 4 binary number to 1 hexadecimal digit.
853710 = 215916
 Question 163

Which of the following is a recursive algorithm to convert a positive decimal integers into equivalent binary integers?

 A B C D Question 163 Explanation:
Let decimal number be 10.
(10)10 = (?)2
Step 1 : 10 % 2 which is equal to 0 + 10 * ( 10/2 ) % 2
Step 2 : 5 % 2 which is equal to 1 + 10 * ( 5 / 2) % 2
Step 3 : 2 % 2 which is equal to 0 + 10 * ( 2 / 2 ) % 2
Step 4 : 1 % 2 which is equal to 1 + 10 * ( 1 / 2 ) % 2
Output : 1010
Therefore (10)10 = (1010)2
 Question 164

What is the minimum number of 2 input NOR gates to implement the Boolean function (XY+Z)?

 A 8 B 5 C 3 D 7
Question 164 Explanation:
(XY+Z)
(X+Z)(Y+Z) // using distributive
((X+Z)’ + (Y+Z)’)’
So, we require Three 2-input NOR gates Question 165
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
 A Clock input of all flip flops B J and K input of one flip flop C J and K input of all flip flops D Clock input of one flip flops
Question 165 Explanation:
• In a ripple counter using edge-triggered JK flip-flops the pulse input is applied to clock input of one flip flop then
• First Flip flop is clocked and the rest are clocked from their previous flip flop's output. above diagram is 3 bit ripple counter using JK flip flop Here you can see in diagram Q0,Q1 applied to clock input of one flip flop
 Question 166
How many 2-input multiplexers are required to construct a 2​ 10​ input multiplexer?
 A 1023 B 31 C 10 D 127
Question 166 Explanation:
To construct 210 x 1-MUX using 2x1 MUX:

1024/2 = 512
512/2=256
256/2=128
128/2=64
64/2=32
32/2=16
16/2=8
8/2=4
4/2=2
2/2=1

Now add all the values  512+256+128+64+32+16+8+4+2+1=1023 MUX

Outcome from the question : In general, The number of N-input Multiplexers needed to create a M-input multiplexer (M > N) is, Question 167
The number of columns in a state table for a sequential circuit with 'm' flip flops and 'n' input is
 A M+n B M+2n C 2m+n D 2m+2n
Question 167 Explanation:
Each of any  M flip-flops, we have to write the present state  as the next state of the flip flop.
IF M=1, we have two entries, 1 for present state and 1 for next state.
So, for M flip-flops, there will be 2M columns for flip-flop state information.
If there is one input,  then there will be 1 column.
So, for N input, we should have N columns.
Total columns in state table will be = 2M + N
 Question 168
A decimal has 25 digits. the number of bits needed for its equivalent binary representation is approximately
 A 50 B 74 C 40 D 60 E None
Question 168 Explanation:
Maximum 25 digit decimal number = 1025 – 1
Maximum x bit binary number = 2x – 1
1025 – 1 = 2x – 1
1025  = 2x
Apply log on both sides then we get
log 21025 = log 22x
log 21025 = x log 22
log 21025 = x
x = 25 log 210
x = 25 x 3.322
x = 83.6 (approximately 84)

Minimum 84 bits are required to 25 digit number
 Question 169
A sequential circuit using D flip flop and logic gates is shown in figure, Where X and Y are the inputs and Z is the output. The circuit is A S-R flip flop with inputs X=R and Y=S B S-R flip flop with inputs X=S and Y=R C J-K flip flop with inputs X=J and Y=K D J-K flip flop with X=k and Y=J
 Question 170
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
 A R=10 ns, S=40ns B R=40ns, S=10ns C R=10ns, S=30ns D R=30 ns, S=10ns
Question 170 Explanation:
In Ripple counter each Filp Flop waits for its previous Filp Flop's output
So, In ripple counter delay will be 4*Td = 4*10 = 40ns

In Synchronous counter all Filp Flop's are triggered by same clock So all four Filp Flop's will give output at a time
So, Worst delay will be equal to 10 ns.

Therefore R=40ns S=10ns
 Question 171
The smallest integer that can be represented by an 8-bit number in 2's complement form is:
 A -256 B -128 C -127 D 0
Question 171 Explanation:

For n bit 2’s complement numbers, range of number is -(2(n-1)) to +(2(n-1)-1)

The Smallest integer that can be represented by an 8-bit number in 2’s complement = -(2(n-1))
= -(2(8-1)) = -(27)
= - 128
• Number of distinct numbers that can be represented using n bits = 2n
• In Unsigned numbers these corresponds to numbers from 0 to 2n−1.
• In Signed numbers in 1′s complement or sign magnitude representation, these corresponds to numbers from −(2n−1−1) to ( 2n−1 −1 )   with 2 separate representations for 0.)
• In Signed numbers in 2′s complement representation, these corresponds to numbers from (−2n−1 ) to (2n−1 −1 )   with a single representation for 0.
 Question 172
The number (25)6 base 6 is equivalent to __ in binary number system
 A 11001 B 10001 C 11000 D 10000
Question 172 Explanation:
Step 1 : convert base 6 to decimal
(25)6 = 2*61+5 = (17)10

Step 2 : Now convert decimal to binary
(17)10 = (10001)2

Step 3 : (25)6 = (10001)2
 Question 173
To load a byte of data parallelly into a shift register with a synchronous load, there must be__
 A One clock pulse B One clock pulse for each 1 in the data C Eight clock pulses D One clock pulse for each 0 in the data
Question 173 Explanation:
• Sequential device loads the data present on its inputs and then moves or "shifts" it to its output once every clock cycle, hence the name Shift Register.
• A shift register basically consists of several single bit "D-Type Data Latches", one for each data bit, either a logic “0” or a “1”
• Connected together in a serial type daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on.
 Question 174
Shifting a register content to left by one bit is equivalent to____
 A Division by 2 B Addition by 2 C Multiplication by 2 D Subtraction by 2
Question 174 Explanation:
• Shifting a binary number to the left by 1 position, it is equivalent to the multiplication of number by 2.
• Shifting a binary number to the right by 1 position, it is equivalent to dividing the number by 2.
 Question 175
What shall be the 2’s complement represented of -24 in a 16 bit computer?
 A 1111 1111 1110 1011 B 1111 1111 1110 1001 C 1111 1111 1110 0111 D 1111 1111 1110 1000
Question 175 Explanation:
Step 1:  (24)10 = (0000 0000 0001 1000)2

Step 2 : convert into 1'complement then add 1 to  it then you get 2'complement
0000 0000 0001 1000 = 1111 1111 1110 0111

Step 3 : add 1 to it then

step 4 : 2'complement will be 1111 1111 1110 1000
 Question 176
Which of the following is/are wrong?
a) RAM and ROM are volatile memories
b) ROMs,PROMs and EPROMs are non volatile memories
c) RAM and Dynamic RAM are same
d) A random access memory(RAM) is a read write memory
 A (a) and (b) B (a) and (c) C (a) and (d) D (c) and (d)
Question 176 Explanation:
option (A) RAM and ROM are volatile memories - FALSE
• In volatile memory, data loses in power off. RAM is volatile memory.
• In non-volatile memory, data remains in the computer even if computer is switched off . ROM(Read Only Memory) is non-volatile memory.
option (B) ROMs, PROMs and EPROMs are non volatile memories - TRUE
• ROM(Read Only Memory) is non-volatile memory.
• A programmable read-only memory (PROM) is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. (eFUSEs can also be used) It is one type of ROM (read-only memory). The data in them are permanent and cannot be changed. so it is  non-volatile
• An EPROM (rarely EROM), or erasable programmable read-only memory, is a type of programmable read-only memory (PROM) chip that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile.
option (C) RAM and Dynamic RAM are same - FALSE
• DRAM = Primary Memory
• SRAM = Cache
option (D) A random access memory(RAM) is a read write memory - True
• RAM is also called read write memory or Main memory or primary memory
So  option (A) and option (D) are TRUE
 Question 177
Exclusive OR(XOR) is a special gate whose output is 1 only if:
 A All inputs are 0 B All inputs are 1 C Odd numbers of inputs are 1 D Even number of inputs are 1
Question 177 Explanation:
1. Exclusive OR(XOR) whose output is 1 only if : Inputs are different
2. XOR is 1 of all numbers of 1's in the range is odd,
3. Exclusive OR(XOR) whose output is 0 only if  : Inputs are same
4. XOR is o of all numbers of 1's  in the range is even,
 Question 178
Which of the following flipflops does not have a problem of race condition?
 A T flip flop B JK flip flop C Clocked-RS flip flop D Clocked D flip flop
Question 178 Explanation:
• When the S and R inputs in SR flipflop is 1, then the output becomes unstable and it is known as race condition.
• When the S and R inputs in SR flipflop is  1 and then the input is changed to any other condition, then the output becomes unpredictable and this is also called the race condition.
• T- flip flop has racing condition. When clock input is 1 and T input is 1 it will toggles the previous state. As long as the clock input is 1, it will toggles the previous state.
• JK Master slave flip flop avoid racing. as long as clock is high for the input conditions and j=1 and k=1 the output complements its output from 1 to 0 and 0 to 1
 Question 179
A device which converts BCD to seven segment is called____
 A Encoder B Decoder C Decoder D Demultiplexer
Question 179 Explanation:
• Decoder is an essential component in BCD to seven segment decoder.
• A decoder is a combinational logic circuit mainly used for converting a BCD to an equivalent decimal number.
• It can be a BCD to seven segment decoder.
 Question 180
In single-precision, double-precision and extended-precision representation of floating point numbers, as defined by ANSI/IEEE standard 754-1985, the no.of bits used are____ respectively.
 A 32,64 and 80 B 32,64 and 128 C 16,32 and 64 D 16,32 and 80
Question 180 Explanation: Single precision Double precision Extended precision is 3rd format which is 80 bit word
 Question 181
The simplified form of the boolean expression:(AB’(C+BD)+A’B’)C is:
 A B’C B A’B’C C AB’C D A’BC
Question 181 Explanation:
(AB’(C+BD)+A’B’)C
(AB'C +AB'BD + A'B') C
(AB'C +0 + A'B' )C   // BB'=0
(AB'C + A'B' )C
AB'C + A'B' C
B' C(A+A')  Taking B' C  as common
B' C(1)
B'C
 Question 182
A decimal has 25 digits. the number of bits needed for its equivalent binary representation is approximately
 A 50 B 74 C 40 D None of the above
Question 182 Explanation:
Maximum 25 digit decimal number = 1025 – 1
Maximum x bit binary number = 2x – 1
1025 – 1 = 2x – 1
1025  = 2x
Apply log on both sides then we get
log 21025 = log 22x
log 21025 = x log 22
log 21025 = x
x = 25 log 210
x = 25 x 3.322
x = 83.6 (approximately 84)

Minimum 84 bits are required to 25 digit number
 Question 183
Which of the following is minimum error code?
 A Octal code B Binary Code C Gray code D Excess-3 Code
Question 183 Explanation:
• The gray code which is also known as the reflected binary code is a binary numeral system where two successive values differ in only one bit position at a time.
• Gray codes are less error-prone for mechanical devices that involve making and breaking electrical circuits because they only change in one bit position at a time.
• Gray code  considered as the minimum error code.
 Question 184
The possible number of boolean function of 3 variables X,Y and Z such that f(X,Y,Z)=f(X',Y',Z')
 A 8 B 16 C 64 D 32
Question 184 Explanation:
Total number of boolean functions are possible 22n =223=256

But in this they are asking Number of boolean functions which satisfies this f(X,Y,Z)=f(X',Y',Z') condition

• f(X,Y,Z) =f(X',Y',Z')
• (0,0,0)  = (1,1,1)
• (0,0,1)  = (1,1,0)
• (0,1,0)  = (1,0,1)
• (0,1,1)  = (1,0,0)
• (1,0,0)  = (0,1,1)
• (1,0,1)  = (0,1,0)
• (1,1,0)  = (0,0,1)
• (1,1,1)  = (0,0,0)
it means different boolean functions f(x,y,z) such that f(x,y,z)=f(x',y',z') for all values of the varable x,y,z

there can be 24 =16 different possible functions with 3 varable x,y,z,0 or 1

similarly there can be 16 diffent possible functions with x',y'z',0 or 1 but each function in x,y,z is equal to the function x'y'z'
 Question 185
If the original size of data is 40 then after adding error detection redundancy bit the size of data length is
 A 26 B 36 C 46 D 56
Question 185 Explanation:
Redundant bits are extra binary bits that are generated and added to the information-carrying bits of data transfer to ensure that no bits were lost during the data transfer.

Number of redundant bits can be calculated by using the below formula:

2r ≥ m + r + 1

where, r = redundant bit, m = data bit

So, given r=6, m =40

64 > 40 + 6 +1

Therefore size of codeword becomes m+r = 40 +6  =46
 Question 186
A sequential circuit using D flip flop and logic gates is shown in figure, Where X and Y are the inputs and Z is the output. The circuit is A S-R flip flop with inputs X=R and Y=S B S-R flip flop with inputs X=S and Y=R C J-K flip flop with inputs X=J and Y=K D J-K flip flop with X=k and Y=J
 Question 187
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
 A R=10 ns, S=40ns B R=40ns, S=10ns C R=10ns, S=30ns D R=30 ns, S=10ns
Question 187 Explanation:
In Ripple counter each Filp Flop waits for its previous Filp Flop's output
So, In ripple counter delay will be 4*Td = 4*10 = 40ns

In Synchronous counter all Filp Flop's are triggered by same clock So all four Filp Flop's will give output at a time
So, Worst delay will be equal to 10 ns.

Therefore R=40ns S=10ns
 Question 188
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
 A Clock input of all flip flops B J and K input of one flip flop C J and K input of all flip flops D Clock input of one flip flops
Question 188 Explanation:
• In a ripple counter using edge-triggered JK flip-flops the pulse input is applied to clock input of one flip flop then
• First Flip flop is clocked and the rest are clocked from their previous flip flop's output. above diagram is 3 bit ripple counter using JK flip flop Here you can see in diagram Q0,Q1 applied to clock input of one flip flop
 Question 189
Consider an arbitrary number system with the independent digits as 0,1 and X. What is the radix of this number system?
 A 1 B 2 C 3 D 4
Question 189 Explanation:
• The radix of the proposed number system is 3.
• The first 10 numbers in this number system would be 0, 1, X, 10, 11, 1X, X0, X1, XX and 100
 Question 190
 A Exclusive NOR gate B NAND gate C AND gate D OR gate
Question 190 Explanation: Question 191
 A Half adder B Half subtractor C Full adder D Full Subtractor
Question 191 Explanation: Question 192
A/an _____, also called a data selector, is a combinational circuit with more than on input line, one output line and more than one selection line.
 A De multiplexer B Multiplexer or MUX C Operational amplifier D Integrated circuit
Question 192 Explanation:
• Multiplexer is a combinational circuit which have many data inputs and single output depending on control or select inputs.​
• For N input lines, log2n  selection lines, or we can say that for 2n input lines, n selection lines are required.
• Multiplexers are also known as "Data n selector, Parallel to serial convertor, Many to one circuit, Universal logic circuit​".
 Question 193
Determine the function performed by the combinational circuit of the given figure.
 A 4 to 1 multiplexer B 8 to 1 multiplexer C 16 to 1 multiplexer D 32 to 1 multiplexer
Question 193 Explanation:
Required mux 4*1
4/2 =2
2/2 =1
∴ 2+1 =3

∴ 3 2*1 mux are required to implement 1 4*1 mux

Outcome from the question : In general, The number of N-input Multiplexers needed to create a M-input multiplexer (M > N) is, Question 194
Determine the size of PROM required for implementing the 16 to 1 multiplexer
 A 1Mx1 B 2Mx1 C 8Mx1 D 32mx1
Question 194 Explanation:
Generally PROM Consists of n input and m output lines represented as  2x m  PROM

For implementing  any circuit with n-input , m-output then size of the  PROM will be 2x m size PROM

In this question we have to implement 16 * 1 mux So inputs are 16 + (4 selection lines ) = 20

So n=20 and m=1

PROM size =220 x  1=  1M x  1
 Question 195
The hamming(7,4) code for 0000 using even parity is
 A 0000000 B 1111111 C 2222222 D 12121212
Question 195 Explanation:
• The four data bits — assembled as a vector p — is pre-multiplied by G (i.e., Gp) and taken modulo 2 to yield the encoded value that is transmitted.
• The original 4 data bits are converted to seven bits (hence the name "Hamming(7,4)") with three parity bits added to ensure even parity using the above data bit coverages.
• Given data  0000 by using  Hamming(7,4) we are sending  0000 000
 Question 196
Determine the number of programmable inter connections in the following programmable logic device-PAL device with eight input variables, 16 AND gates and four OR gates
 A 384 B 512 C 256 D 128
Question 196 Explanation:
Discuss this solution in Discussion Forum
 Question 197
The reduced expression for the following expression using a karnaugh map F(W,X,Y,Z)=Σ(0,4,8,12) is:
 A YZ B Y’Z’ C Y+Z D Y’+Z’
Question 197 Explanation: Question 198
 A Diode B Transistor C Diode transistor D Resistor
Question 198 Explanation:
Above given diagram is a combination of both Diode and Transistor.
• Diode is a two-terminal device that allows electric current to flow in only one direction. Thus, it is the electronic equivalent of a check valve or a one-way street. It is commonly used to convert an Alternating Current (AC) into a Direct Current (DC).
• Transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. You can think as relays without any moving parts because they can turn something ‘on’ or ‘off’ without any movement.
• Resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. In electronic circuits, resistors are used to reduce current flow, adjust signal levels, to divide voltages, bias active elements, and terminate transmission lines, among other uses.
 Question 199
The reduced expression for the following expression using a karnaugh map F(W,X,Y,Z)=Σ(0,4,8,12) is:
 A YZ B Y’Z’ C Y+Z D Y’+Z’
Question 199 Explanation: Question 200
In a Schmitt trigger inverter circuit, the two trip points are observed to occur ar 1.8 and 2.8V. At what input voltage levels will this device make
(a) HIGH-to-LOW transition and
(b) LOW-to-HIGH transition?
 A 2.8V & 1.8V B 3V & 2V C 4V & 2.2V D 2.6V & 1.5V
Question 200 Explanation:
2.8V & 1.8V
 Question 201
A combinational logic circuit that is used when it is desired to send data from two more source through a single transmission line is known as__
 A Demultiplexer B Encoder C Decoder D Multiplexer
Question 201 Explanation:
• Multiplexer is a combinational circuit which have many data inputs and single output depending on control or select inputs.​
• For N input lines, log2n  selection lines, or we can say that for 2n input lines, n selection lines are required.
• Multiplexers are also known as "Data n selector, Parallel to serial convertor, Many to one circuit, Universal logic circuit​".
 Question 202
The number of bits required to represent decimal number 4096 in binary form is___
 A 16 B 10 C 12 D 13
Question 202 Explanation:

(4096)16 =( ? )2

Step 1: Inorder to convert to binary Divide (4096)10 successively by 2 until the quotient became 0
• 4096/2 = 2048, ∴ Remainder will be is 0
• 2048/2 = 1024, ∴ Remainder will be is 0
• 1024/2 = 512, ∴ Remainder will be is 0
• 512/2 = 256, ∴ Remainder will be is 0
• 256/2 = 128, ∴ Remainder will be is 0
• 128/2 = 64, ∴ Remainder will be is 0
• 64/2 = 32, ∴ Remainder will be is 0
• 32/2 = 16, ∴ Remainder will be is 0
• 16/2 = 8, ∴ Remainder will be is 0
• 8/2 = 4, ∴ Remainder will be is 0
• 4/2 = 2, ∴ Remainder will be is 0
• 2/2 = 1, ∴ Remainder will be is 0
• 1/2 = 0, ∴ Remainder will be is 1
Step 2: Now Read  the bits from the bottom ( MSB) to top (LSB) as 1000000000000
Total 13 bits are required to represent 4096
 Question 203
The term sum of product in boolean algebra means
 A The AND function of several AND functions B The AND function of several OR functions C The OR function of several AND functions D The OR function of several OR functions
Question 203 Explanation:
There are two types of canonical forms:
• Sum-of-min terms or Canonical SOP
• Product-of- max terms or Canonical POS
A sum-of-products form can be formed by adding (or summing) two or more product terms using a Boolean addition operation.

Here the product terms are defined by using the AND operation and the sum term is defined by using OR operation.

The sum-of-products form is also called as Disjunctive Normal Form as the product terms are ORed together and Disjunction operation is logical OR.

Sum-of-products form is also called as Standard SOP.
 Question 204
Based on the current technology,___ is the fastest logic family
 A CMOS B TTL C MOS D ECL
Question 204 Explanation:
• The full form of ECL is emitter-coupled logic.
• ECL is the fastest of all the logic families because of the emitters of many transistors are coupled together which results in the highest transmission rate.
 Question 205
How many bits are used in the exponent part of IEEE single precision for the representation of floating point numbers?
 A 32 bits B 8 bits C 16 bits D 24 bits
Question 205 Explanation: Single precision Double precision Extended precision is 3rd format which is 80 bit word
 Question 206
In a positive edge triggered JK flip flop, a low J and a low K produces
 A No change B Low state C High state D Toggle state
Question 206 Explanation:
 Question 207
The boolean expression (A+C)(AB'+AC)(AC'+B') can be simplified as
 A A'B+BC B AB' C AB+BC D AB+A'C
Question 207 Explanation:
•  (A+C)(AB'+AC)(AC'+B')
• (AB'+AC + AB'C + AC) (AC'+B') // USING DISTRIBUTIVE
• (AB'+AC + AB'C ) (AC'+B')
• (AC+ AB'(1+1C))(AC'+B')   // taking ab' as common
• (AC+ AB')(AC'+B')   // 1*c =c and c+1=1
• AC(AC') +ACB' + AB'AC' + AB' // USING DISTRIBUTIVE
• ACC' +ACB' + AB'AC' + AB'
• ACB' + AB'C' + AB'  // C*C'= 0 and 0*A=0
•  AB'(C+C') + AB'  // TAKING AB' COMMON
• AB' + AB'   // C+C' =1
• AB'
 Question 208
What is the octal equivalent of the hexadecimal number 132A?
 A 46252 B 11450 C 11452 D 45250
Question 208 Explanation:
(132A)16 = (11452)8

Step 1:  obtain the equivalent group of four binary digits.
• (1)16 = (0001)2
• (3)16 = (0011)2
• (2)16 = (0010)2
• (A)16 = (1010)2
Step 2: Group each value and remove zeros at left (if necessary) to get the partial result in base 2
0001 0011 0010 1010 = 1001100101010
(132A)16 = (1001100101010)2

Step 3: Rearrange all the digits in sets of three starting from the LSB (far right). Add zeros to the left of the last digit if there aren't enough digits to make a set of three.
001 001 100 101 010

Step 4: Use the table below to convert each set of three into an octal digit. In this case,
001=1, 001=1, 100=4, 101=5, 010=2.
So, 11452 is the octal equivalent of hexadecimal number 132A
 Question 209
 A 4,0 B 1,3 C 2,2 D 3,1
Question 209 Explanation:
• IF 16- bit operation then we need 15-FA,1-HA
• IF 17- bit operation then we need 16-FA,1-HA
• In general for n-bit operation : (n-1)FA and 1-HA are required
To add two 4 bit numbers using minimum gates, the least significant bits of both the numbers can be added using a half adder and for remaining 3 bits of both the numbers, full adders can be used. 1 Half Adder and 3 Full Adders will be required.
 Question 210

The signed 2’s complement representation of -33 is:

 A 11011111 B 00100001 C 01011111 D 10100001
Question 210 Explanation:
Step 1 : (33)10 =(00100001)2
Step 2 : Now get  the 2's complement
Step 3 :   11011110  ( for 1's complement add 1 to it then we get 2's complement)
Step 4:    11011111
 Question 211

Using signed 2’s complement subtraction the result of 11111010-11110011 is:

 A 10000111 B 00000111 C 10001101 D 00001101
Question 211 Explanation:
Step 1 : At first, 2’s complement of the subtrahend is found.
Step 2 : Then it is added to the minuend.
Step 3 : If the final carry over of the sum is 1, it is dropped and the result is positive.
Step 4 : If there is no carry over, the two’s complement of the sum will be the result and it is negative.

Given  11111010 - 11110011 = ( - 6 )  -  ( -13 )

Step 1 : The subtraction is changed to addition by taking the 2' s complement of the subtrahend (-13), giving ( + 13)
for getting  2' s complement  first get 1' s complement then add 1 to it

11110011
0000 1100 (1' s complement )
+1
----------------
0000 1101 (2' s complement )

Step 2 :
11111010 + 00001101 = 100000111

Step 3 :
Removing the end carry  we got 00000111 (+7)
 Question 212

In boolean algebra, (x ⋀ y)’ = x’ V y’ and (x V y)’ = x’ ⋀ y’ is known as ___ law.

 A Demorgan’s law B Absorption C Dominance D Idempotent
Question 212 Explanation:
In propositional logic and Boolean algebra, De Morgan's laws are a pair of transformation rules that are both valid rules of inference

The rules allow the expression of conjunctions and disjunctions purely in terms of each other via negation.

The rules can be expressed in English as:
• the negation of a disjunction is the conjunction of the negations;
• the negation of a conjunction is the disjunction of the negations;
 Question 213
Convert the following octal number into its decimal equivalent: 2374 in octal
 A (10208)10 B (1276)10 C (2374)10 D (1272)10
Question 213 Explanation: Question 214

Which of the following statement/s is/are correct?

• With on-chip decoding, 8 address lines can access 64 memory locations
• With on-chip decoding, 4 address lines can access 64 memory locations
• With on-chip decoding, 8 address lines can access 256 memory locations
• With on-chip decoding, 4 address lines can access 128 memory locations
 A Only A B A and B C Only C D C and D
Question 214 Explanation:
• Decoder is a combinational circuit that has ‘n’  address lines and maximum of 2n  memory locations
• For 8 address lines maximum of 28  = 256 memory locations are possible
 Question 215
Represent the decimal number 3.248*104 into a single precision floating point binary number(using standard format).
 A 0|10001101|11111011100000000000000 B 0|11001101|11111011100000000000000 C 1|11001101|11111011100000000000000 D 0|10001110|11111011100000000000000
Question 215 Explanation:
Step 1 : Convert Given Number into decimal 3.248 x 104  = 32480

Step 2 : Now get its equivalent binary number (32480)10 = (111111011100000 )2

Step 3 : Normalize the binary representation of the number
(111111011100000 ) = 1.11111011100000 * 214

Step 4 :  32 bit single precision IEEE 754 binary floating point representation
Excess 127 = 127 + 14 = 141
Exponent = 10001101
Mantissa = 11111011100000000000000

0 10001101 11111011100000000000000
 Question 216
When used with IC, what does he term QUAD indicate?
 A 2 circuits B 4 circuits C 6 circuits D 8 circuits
Question 216 Explanation:
A quad gate is an IC (integrated circuit or chip) containing four logic gates. The gates can be of any type: AND, OR, XOR, NOT, NAND, NOR, and XNOR. Within any given quad gate, all four of the individual gates are normally of the same type.
 Question 217
Data can be changed from special code to temporal code by using
 A Shift Registers B Counters C Combinational circuits D A/D converters
Question 217 Explanation:
Shift Register in which data gets shifted towards left or right when clock pulses are applied
 Question 218
Words having 8 bits are to be stored in computer memory. The number of lines required for writing into the memory are
 A 1 B 2 C 4 D 8
Question 218 Explanation:
Given Words having 8 bits so 8 are lines required for writing into the memory each line carries 1 bit
 Question 219
Words having 8 bits are to be stored in computer memory. The number of lines required for writing into the memory are
 A 1 B 2 C 4 D 8
Question 219 Explanation:
Given Words having 8 bits so 8 are lines required for writing into the memory each line carries 1 bit
 Question 220
Which is the hexadecimal number equivalent to the octal number 46250
 A 4AC8 B 4CA8 C CCA8 D 4CA4
Question 220 Explanation:
(46250)8 = (4CA8)16
Step 1:  obtain the equivalent group of three binary digits.
• (4)8 = (100)2
• (6)8 = (110)2
• (2)8 = (010)2
• (5)8 = (101)2
• (0)8 = (000)2
Step 2: Group each value of step 1 to make a binary number.
100 110 010 101 000
(46250)8 = (100110010101000)2

Step 3: Now convert the binary number from step 2 to hexadecimal by grouping all the digits of the binary in sets of four starting from the LSB (far right).
0100 1100 1010 1000
Note: add zeros to the left of the last digit if there aren't enough digits to make a set of four.

Step 4: Convert each group of four to the corresponding hexadecimal
0100=4, 1100=C, 1010=A, 1000=8.
(46250)8 = (4CA8)16
 Question 221
If a 3-input NOR gate has 8 input possibilities, how many of those possibilities will result in a HIGH output?
 A 1 B 3 C 7 D 8
Question 221 Explanation:
Output of a NOR gate is high only when all the inputs of the NOR gate will 000
 Question 222
Consider a Boolean function of ‘n’ variables. The order of an algorithm that determines whether the Boolean function produces a output 1 is :
 A Logarithmic B Linear C Quadratic D Exponential
Question 222 Explanation:
• For "n" boolean variables  there are 2n rows in truth table.
• For determines whether the boolean function produces a output 1 for the given function, in worst case it needs to check every possible row → O(2n) which is Exponential
 Question 223
The Octal equivalent of the binary number 1011101011 is :
 A 7353 B 1353 C 5651 D 5657
Question 223 Explanation:
An octal Equivalent of a binary number is obtained by grouping the 3 bits from right to left
001  011  101  011

Now convert these three bits into decimal and that will be
001  011  101  011
1       3      5      3

Octal equivalent of the binary number 1011101011 is : 1353
 Question 224
Let m=(313)​4​ and n=(322)​4​. Find the base 4 expansion of m+n ?
 A (635)​ 4 B (32312)​ 4 C (21323)​ 4 D (1301)​ 4
Question 224 Explanation:
Step 1 : First converting both the number in decimal system.
Given,
m=(313)4
Now convert "m" into decimal
m = 3*42 + 1*41 + 3*40
m = 48 + 4 + 3
m = 52+ 3
m = 55.

Given,
n=(322)4
Now convert "n" into decimal
Now n=3*42 + 2*41 +2*40
n = 48 + 8 +2
n = 58.

m=55, n=58
m + n = 55 + 58
m + n = 113

Step 3 : Finally, Converting addition result which is 113 into Base(4)
```→113 % 4 = 1
113 / 4 = 28
→28 % 4 = 0
28 / 4 = 7
→7 % 4 = 3
7 / 4 = 1
→1 % 4 = 1
1/4 →we can't divide into further it in quant,
So we need to stop here.```
Take the Residue value from bottom to top in-order i.e. 1301
(113)10 = (1301)4
 Question 225
Convert the octal number 0.4051 into its equivalent decimal number.
 A 0.51001 B 0.2096 C 0.52 D 0.4192
Question 225 Explanation:
```(0.4051)8 = 4*8-1 + 0*8-2 + 5*8-3 + 1*8-4
= 0.5100098```
Octal number (0.4051)8 into its equivalent decimal number 0.5100098
 Question 226
The hexadecimal equivalent of the octal number 2357 is :
 A 2EE B 2FF C 4EF D 4FE
Question 226 Explanation:
Step 1 : First Convert the given octal number into binary number
(2357)8 =  (010 011 101 111)2

Step 2 : Now  convert these binary number into hexadecimal by grouping them of 4 from right to left
(010 011 101 111)2 = 0100 1110 1111

Step 3 : Now place the hexadecimal equivalent
i.e.
11 – F
1110 – E
0100 – 4

(2357)8  = ( 4EF)16

 Question 227
If X is a binary number which is power of 2, then the value of X & (X – 1) is :
 A 11....11 B 00.....00 C 100.....0 D 000......1
Question 227 Explanation:
• Number System Properties states that any given number "x" which is powers of 2, is that they have one and only one bit set in their binary representation.
• If the number is neither zero nor a power of two, it will have 1 in more than one place. So if x is a power of 2 then x & (x-1) always will be ZERO (0).
We will go in traditional way :
Let's us assume  X = 24 = 16 =10000
then X - 1 = 16-1 = 15 = 01111
Now, X & (X-1)  = 16 & 15 = 00000

Note : Here, & is a bit-wise AND operator.
Bit-wise AND operator compares each bit of its first operand to the corresponding bit of the second operand. If both bits are 1 's, the corresponding bit of the result is set to 1 . Otherwise, it sets the corresponding result bit to 0 .
 Question 228
The octal number 326.4 is equivalent to
 A (214.2)​ 10​ and (D6.8))​ 16 B (212.5)​ 10​ ​ and (D6.8))​ ​ 16 C (214.5)​ 10​ and (D6.8))​ ​ 16 D (214.5)​ 10​ and (D6.4))​ ​ 16
Question 228 Explanation:
→Converting Octal number (326.4)8 into its equivalent decimal number
```(326.4)8  = 82*3 + 81*2 + 80*6 . 8-1*4
=(214.5)10```

→Converting Octal number (326.4)8 into its equivalent Hexa-decimal

Step 1 : First Convert the given octal number into binary number by represent every digit in 3 bits
(326.4)8 = (011010110.100)2

Step 2 : Now  convert these binary number into hexadecimal by grouping them of 4 from right to left. Pad extra bit if required. Below 0 can be padded after decimal
(011010110.100)2  = 0 1101 0110. 1000

Step 3 : Now place the hexadecimal equivalent
1101    - D
0110    - 6
1000  - 8

(326.4)8  = (D6.8)16

Therefore, Option(C) is correct one.
 Question 229
Which of the following is the most efficient to perform arithmetic operations on the numbers?
 A Sign-magnitude B 1’s complement C 2’s complement D 9’s complement
Question 229 Explanation:
• In 2’s complement representation is a unambiguous for 0 (only positive 0), but Sign-magnitude, one’s complement and nine’s complement are ambiguous representation for 0 (i.e., both positive and negative 0).
• The main advantage of two’s complement over the one’s complement is that there is no double-zero problem plus it is a lot easier to generate the two’s complement of a signed binary number. Therefore, arithmetic operations are relatively easier to perform when the numbers are represented in the two’s complement format
• While we are performing arithmetic operations like addition or subtraction using 1's complement, we need to add an extra carry bit, i.e. 1 to the result to get the correct answer. but incase of 2's complement has no such extra calculation is required
 Question 230
An example of a binary number which is equal to its 2​ ’s complement is :
 A 1100 B 1001 C 1000 D 1111
Question 230 Explanation:
Generally , to get the 2’s complement for the given number first we need to perform 1’s complement of given binary number by simply invert the given number and add  1 to the least significant bit (LSB).

Option(A) : 1010
1's complement = 0101
2's complement = 0110

Option(B) : 0101
1's complement =1010
2's complement = 1011

Option(C) : 1000
1's complement =0111
2's complement = 1000

Option(D) : 1001
1's complement =0110
2's complement = 0111

Therefore, Option(c) is the correct answer.
 Question 231
Which of the following is divisible by 4 ?
 A 100101100 B 1110001110001 C 11110011 D 10101010101010
Question 231 Explanation:
Option(A) : (100101100)​2​ = (300)​10
300%4 = 0. So, 300 is divisible by 4

Option(B) : (1110001110001)​2​ = (7281)​10
7281%4= 1;  So, 7281 is not divisible by 4

Option(C) : (11110011)​2​ = (243)​10
243%4=3.   So, 243 is not divisible by 4

Option(D) : (10101010101010)​2​ = (10,922)​10
10,922%4 = 2.  So, 10,922 is not divisible by 4.

Therefore, Option(A) is correct one
 Question 232
A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?
 A 0.64 B 0.96 C 2 D 0.32
Question 232 Explanation:
Given,
Memory cycle time = 250 nsec
Memory is refreshed 32 times per msec

Number of refreshes in 1 memory cycle = (32 * 250 * 10-9) / 10-3 = 8 * 10-3.
It means in 250 nsec Number of refreshes = 8 * 10-3.

Total Time taken for each refresh = 100 nsec
Time taken for 8 * 10-3 refreshes
= 8 * 10-3 * 100 * 10-9
= 8 * 10-3 * 102 * 10-9
= 8 * 10-10

Percentage of the memory cycle time is used for refreshing
= ( Time taken to refresh in 1 memory cycle / Total time ) * 100
= (8 * 10-10 / 250 * 10-9) * 100
= 0.032 * 10
= 0.32

 Question 233
The hexadecimal equivalent of the binary integer number 110101101 is :
 A D24 B 1 B D C 1 A E D 1 A D
Question 233 Explanation:
Convert the given binary number into hexadecimal equivalent  by grouping them of 4 from right to left and assign alphabet when it exceeds 1001 and pad extra bit if needed.

Step 1 :
Given number = 110101101

(110101101)2 =
0001  1010  1101
1          10       13

Step 2 : Assign alphabet when it exceeds 1001
• 1101  – D
• 1010  – A
• 1         – 1

So, option(D) is correct.
 Question 234
 A (A+C).D+B B (A+B).C+D C (A+D).C+B D (A+C).B+D
Question 234 Explanation: We got the expression as B + CD + AD.
which can be reduced it as B + D ( A + C )
 Question 235
The Karnaugh map for a Boolean function is given as The simplified Boolean equation for the above Karnaugh Map is
 A AB + CD + AB’ + AD B AB + AC + AD + BCD C AB + AD + BC + ACD D AB + AC + BC + BCD
Question 235 Explanation: Question 236
Consider the following statements :
(a) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(b) Optimal boolean expressions may not correspond to simplest networks.
(c) Choosing essential blocks first in a Karnaugh map and then greedily choosing the largest remaining blocks to cover may not give an optimal expression.
Which of these statement(s) is/are correct ?
 A (a) only B (b) only C (a) and (b) D (a), (b) and (c)
Question 236 Explanation:
Option(A):Boolean expressions and logic networks correspond to labelled acyclic digraphs : True
Refer : https://en.wikipedia.org/wiki/Propositional_directed_acyclic_graph

Option(B) : Optimal boolean expressions may not correspond to simplest networks : True

Option(C) : Choosing essential blocks first in a Karnaugh map and then greedily choosing the largest remaining blocks to cover may not give an optimal expression : True
The Karnaugh map (KM or K-map) is a method of simplifying Boolean algebra expressions and it can reduce logic functions more quickly and easily compared to Boolean algebra. By reduce we mean simplify, reducing the number of gates and inputs.
 Question 237
Upto how many variables, can the Karnaugh map be used ?
 A 3 B 4 C 5 D 6
Question 237 Explanation:
• In one dimensional map which can be used to simplify an expression in two variables.
• In two-dimensional map which can be used for up to four variables.
• In three-dimensional map which can be used for up to  six variables.
 Question 238
 A A ⋅ B B AB + BC + CA C _______ B⨁C D A . B . C
Question 238 Explanation: Note : None of the options are matching
 Question 239
A Boolean function F is called self-dual if and only if  F(x1, x2, … xn) = F(͞x1,͞x2, …͞xn)  How many Boolean functions of degree n are self-dual ?
 A 2n B (2)2^n C (2)n^2 D (2)(2^(n-1))
Question 239 Explanation:
Self-dual function conditions are
• The function must be a Neutral Function.
• The function must not contain any mutually exclusive terms.
Number of self-dual functions with n variables = 2 2 n-1

Where n = number of Boolean variables in the function.
• For a function to be a self-dual function, the function must be a neutral function and not contain any mutually exclusive terms. .
• For a function to be a neutral function, number of minterms must be equal to number of maxterms.
• So, we have to select half of them i.e. 2n / 2 = 2n-1 terms.
• Now, for each of these terms, we have 2 options whether it can be included  or not included in the self-dual function.
Therefore, Number of self-dual functions are

= 2 x 2 x 2 x  2 x 2 x……. x 2n-1

= 2 2 n-1
So, option(D) is correct
 Question 240
If F and G are Boolean functions of degree n. Then, which of the following is true ?
 A F ≤ F + G and F G ≤ F B G ≤ F + G and F G ≥ G C F ≥ F + G and F G ≤ F D G ≥ F + G and F G ≤ F
Question 240 Explanation:
Let us consider  F & G be two Boolean function of degree 2

Total Boolean function with degree n = 22n

Total Boolean function with degree 2 = 222=16 Boolean function

F2  → F & G2 → G

F having 16 Boolean functions and G having 16 Boolean functions.

Option(A)  : F + G= 16+16 = 32 Boolean functions  and F*G= 16*16 =256 Boolean functions.
F ≤ F + G and F*G ≤ F FALSE because F *G > F

Option(B) : G ≤ F + G and F*G ≥ G TRUE
F + G= 16+16 = 32  Boolean functions and F*G= 16*16 =256 Boolean functions.

Option(C) : F ≥ F + G and F *G ≤ F - FALSE
F + G= 16+16 = 32  Boolean functions and F*G= 16*16 =256 Boolean functions.

Option-D : G ≥ F + G and F *G ≤ F - FALSE
F + G= 16+16 = 32  Boolean functions and F*G= 16*16 =256 Boolean functions.
 Question 241
The minimum number of two input NAND gates required to implement the Boolean function μ = AB'C is
 A 2 B 3 C 5 D 6
Question 241 Explanation: Total 5 NAND gates are required to Implement Boolean function μ = AB'C
 Question 242
How many different Boolean functions of degree 4 are there ?
 A 24 B 28 C 212 D 216
Question 242 Explanation:
There are 22n different Boolean functions of degree n because
• With n variables there are 2n different n tuples of 0's and 1's
• Each tuple is assigned 0 or 1
With degree 4 there are 224 = 216 different Boolean functions are possible. Question 243
The total number of possible Boolean functions involving ‘n’ Boolean variables is
 A Infinitely many B N​ n C N​ 2 D None of the above
Question 243 Explanation:
There are 22n different Boolean functions on ‘n’ Boolean variables.
Either a particular combination out of the 2n entries in a truth table is true, or false. Therefore, there are 22n total combinations are possible. Question 244
The dual of the switching function x+yz is :
 A X+yz B X + yz C X(y+z) D X(y+z)
Question 244 Explanation:
The dual of expression is obtained by interchanging AND with OR, OR with AND and  0’s with 1’s and  1’s with 0’s . But literals itself are not going to get complimented

So, The dual of x + yz    is    x(y+z)

 Question 245
In RS flip-flop, which of the following values of R and S causes race condition?
 A R=0,S=0 B R=0,S=1 C R=1,S=0 D R=1,S=1
Question 245 Explanation: Question 246
A binary 3 bit down counter uses J-K flip-flops, FF​i with inputs J​i , K​i and outputs Q​i , i=0,1,2 respectively.
The minimized expression for the input from following, is
I. J​0​ = K​0​ = 0
II. J​0​ = K​0​ = 1
III. J​1​ = K​1​ = Q​0
IV. J​1​ = K​1​ =Q’0
V. J​2​ = K​2​ = Q​1​ Q​0
VI. J​2​ = K​2​ = Q’​1​ Q’​0
 A I,III,V B I,IV,VI C II,III,V D II,IV,VI
Question 246 Explanation:
 Question 247
Essential hazards may occur in :
 A Combinational logic circuits B Synchronous sequential logic circuits C Asynchronous sequential logic circuits working in the fundamental mode D Asynchronous sequential logic circuits working in the pulse mode
Question 247 Explanation:
Essential Hazards
• In designing asynchronous sequential circuits, care must be taken to conform to certain restrictions and precautions to ensure that the circuits operate properly.
• The asynchronous sequential circuits must be operated in fundamental mode with only one input changing at any time and must be free of critical races. In addition, there is one more phenomenon called a hazard that may cause the circuit to malfunction.
• Essential hazard is another Type of hazard that may occur in asynchronous sequential circuits
• This type of hazard is caused by unequal delays along two or more paths that originate from the same input.
• An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path may cause such a hazard.
• Essential hazards cannot be corrected by adding redundant gates as in static hazards.
• The problem that they impose can be corrected by adjusting the amount of delay in the affected path.
• To avoid essential hazards, each feedback loop must be handled with individual care to ensure that the delay in the feedback path is long enough compare d with delays of other signals that originate from the input terminals.
 Question 248
Consider the following sequence of instructions :
a=a⊕b, b=a⊕b, a=b⊕a
This Sequence
 A Retains the value of the a and b B Complements the value of a and b C Swap a and b D Negates values of a and b
Question 248 Explanation:
Given sequence,
1. a=a⊕b,
2. b=a⊕b,
3. a=b⊕a

a=a⊕b      ∴ seq 1
b=a⊕b      ∴
seq 2
b=a⊕b⊕b  ∴ a=a⊕b
b=a⊕0        ∴ b⊕b=0
b=a              ∴  a⊕0 =a

a=b⊕a          seq 3
a=a⊕b⊕a    ∴ b=a⊕b (or) b=a and a=a⊕b
a=0⊕b
a=b

∴ Retains the value of the a and b. So, option(A) is correct.
 Question 249
The logic expression x’yz’+x’yz+xyz’+xyz reduces to :
 A X’z B Xyz C Y D Yz
Question 249 Explanation:
1. x’yz’+x’yz+xyz’+xyz
2. x’yz’+x’yz+xy(z'+z)  ∴ Taking xy as common
3. x’yz’+x’yz+xy(1)        ∴ z'+z =1
4. x’yz’+x’yz+xy             ∴ xy * 1 =xy
5. x’y(z’+z) + xy        ∴ Taking x’y as common
6. x’y + xy
7. y (x' + x)                ∴ Taking y as common
8. y
Alternative : By Using K-map Question 250
The dual of a Boolean expression is obtained by interchanging
 A Boolean sums and Boolean products B Boolean sums and Boolean products or interchanging 0’s and 1’s C Boolean sums and Boolean products and interchanging 0’s & 1’s D Interchanging 0’s and 1’s
Question 250 Explanation:
The dual of a Boolean expression is obtained by interchanging sums and products and interchanging 0 and 1.

For example :
• The dual of xy' + 1 is (x + y') · 0
• The dual of x(y+0) and x'.1 +(y'+z) is x+(y.1) and (x'+0)(y'z)
 Question 251
(A + B) (AB)' is equivalent to
 A A ⊕ B B A ʘ B C (A ⊕ B) ʘ A D (A ʘ B) ⊕ A
Question 251 Explanation:
Given,
(A + B) (AB)'
(A + B) (A' + B')
AA' + AB' + BA' + BB'
0 + AB' + A'B +0
AB' + A'B
A ⊕ B
 Question 252
AB+(A+B)'  is equivalent to
 A A ⊕ B B A⨀B C (A ⊕ B) ʘ A D (A ʘ B) ⊕ A
Question 252 Explanation:
AB+(A+B)'
AB + A' B'
A⨀B
 Question 253
The boolean expression x'y'z+yz+xz is equivalent to:
 A X B Y C Z D X+y+z
Question 253 Explanation:
Given boolean expression  is (x'y'z+yz+xz)
=z(x'y'+y+x)  ∴  Taking z as common
Now Applying distributive law (a+bc) = (a+b)(a+c)
=z( (y+y')(x'+y)+x )
=z( (x'+y)+x ) ∵(y+y'=1)
=z( x'+y+x )
=z(1+y) ∵ x'+x = 1
=z(1) ∵(1+y=1)
=z.1  ∵ 1 * z = z
=z
 Question 254
The simplified form of the Boolean expression (X + Y + XY) (X + Z) is
 A X + Y + ZX + Y B XY – YZ C X + YZ D XZ + Y
Question 254 Explanation:
(X + Y + XY) (X + Z)
(X + Y(1+X) ) (X + Z)  ∴ Taking Y as common
(X + Y) (X + Z)
XX + XZ + XY +YZ
X + XZ + XY +YZ
X ( 1 + Z + Y ) + YZ   ∴ Taking X as common
X + YZ                         ∴ 1 + ANYTHING = 1
 Question 255
Simplified form of Boolean expression xy + (~x)z + yz is :
 A Xy+(~x)z. B (~x)y+(~x)z. C (~x)y+xz. D Xy+xz.
Question 255 Explanation: Question 256
If A⊕B=C , then :
 A A ⊕ C = B B B ⊕ C = A C A ⊕ B ⊕ C = 1 D A ⊕ B ⊕ C = 0 E NONE
Question 256 Explanation:
Given expression is  A⊕B=C

Option (A) :  True
A⊕C
=A⊕(A⊕B)  ∴  C=A⊕B
=(A⊕A)⊕B  ∴ Closed under Associative law
=0⊕B            ∴ XOR always 0 for same input
=B

Option(B) : True
B⊕C
= B⊕(A⊕B)  ∴  C=A⊕B
= B⊕(B⊕A)  ∴ Closed under Commutative law
= (B⊕B)⊕A    ∴ Closed under Associative law
= 0⊕A            ∴ XOR always 0 for same input
= A

Option(C) : False
A⊕B⊕C
= A⊕B⊕(A⊕B)
= A⊕B⊕(B⊕A)
= A⊕(B⊕B)⊕A
= A⊕0⊕A
= A⊕A
= 0

Option(D) :  True
A⊕B⊕C = 0

Therefore, option(A), option(B) and (D) are true.
 Question 257
​ Perform the following operation for the binary equivalent of the decimal numbers  (-14)10+(-15)10 The solution in 8 bit representation is :
 A 11100011 B 00011101 C 10011101 D 11110011
Question 257 Explanation:
Step 1 : Perform arithmetic calculations
(−14)10+(−15)10 = (-29)10

Step 2 : Convert 29 into binary number
(29)10 = 0001 1101

Step 3 : But the number is negative. So, Take 1’s complement  and 1 to it
0001 1101
1110 0010 +1  = 11100011
(-29)10  = 11100011

 Question 258
In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be _____ on the rising edge of the clock.
 A No change B Set C Reset D Toggle
Question 258 Explanation:
In a positive-edge-triggered JK flip-flop, If J = 1 and K = 1 , The output continuously Toggles from 1 to 0 and 0 to 1. At the end Output is indeterminate. This condition is called as Race around Condition. This happens when Propagation Delay is less than the Pulse width.
 Question 259
In RS flip-flop, the output of the flip-flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse if :
 A S=R=1 B S=0, R=1 C S=1, R=0 D S=R=0
Question 259 Explanation: Question 260
 A 1,3 B 2,2 C 3,1 D 4,0
Question 260 Explanation:
• IF 16- bit operation then we need 15-FA,1-HA
• IF 17- bit operation then we need 16-FA,1-HA
• In general for n-bit operation : (n-1)FA and 1-HA are required
• If we want to add two n- bit binary adders then it requires 1 half adder and n-1 full adder to complete the circuit.
• To add two 4 bit numbers using minimum gates, the least significant bits of both the numbers can be added using a half adder and for remaining 3 bits of both the numbers, full adders can be used. 1 Half Adder and 3 Full Adders will be required.
 Question 261
Consider a full - adder with the following input values:

(A) x = 1, y = 0 and C​i​ (carry input) = 0
(B) x = 0, y = 1 and C​i​ = 1

Compute the values of S(sum) and C​o​ (carry output) for the above input values.
 A S = 1, C​ o​ = 0 and S = 0, C​ o​ = 1 B S = 1, C​ o​ = 0 and S = 1, C​ o​ = 1 C S = 1, C​ o​ = 1 and S = 1, C​ o​ = 0 D S0 = 1, C​ o​ = 1 and S = 1, C​ o​ = 0
Question 261 Explanation:
In full adder for the inputs x, y and Ci the sum and carry will be :
• So  = x ⊕ y ⊕ Ci
• Co = xy + Ci(x + y)
According to  Statement(i) : Given inputs:  x = 1, y = 0 and Ci= 0
Sum and Carry will be :
• So = 1 ⊕ 0 ⊕ 0 = 1.
• Co = 1*0 + 0(1 + 0) = 0.
According to  Statement(ii) : Given inputs: x = 0, y = 1 and Ci = 1
Sum and Carry will be :
• So = 0 ⊕ 1 ⊕ 1 = 0
• Co = 0*1 + 1(0 + 1) = 1.
 Question 262
The characteristic equation of a T flip-flop is :  _____
[ Note: The symbols used have the usual meaning ]
 A Q​ n+1 =T' Q n​ + T (Q​ n)' B Q​ n+1​ =T+Q​ n C Q​ n+1​ =TQ​ n D Q​ n+1​ = T Q n
Question 262 Explanation: Question 263
When an inventor is placed between both inputs of an S-R flip flop, the resulting flip flop is :
 A JK flip-flop B D-flip-flop C T flip-flop D None of these
 Question 264
The characteristic equation of the D flip-flop is :
 A Q=D B Q=1 C Q=0 D Q(t+1)=D
Question 264 Explanation: Question 265
Which of the following input combination is not desirable for SR flip flop ?
 A S = 0, R = 0 B S = 0, R = 1 C S = 1, R = 0 D S = 1, R = 1
Question 265 Explanation: Question 266
The number of flip-flops required in a decade counter is
 A