# Digital Circuits | Subject Wise

## Digital Circuits Subject Wise

 Question 1
In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz. The frequency of the signal at Q2 is __________ kHz.
 A Fill in the Blank Type Question
Question 1 Explanation:
 Question 2
In the circuit shown, what are the values of F for EN = 0 and EN = 1, respectively?
 A Hi-Z and D B Hi-Z and C 0 and 1 D 0 and D
Question 2 Explanation:
 Question 3
In the circuit shown, A and B are the inputs and F is the output. What is the functionality of the circuit?

 A XOR B SRAM Cell C Latch D XNOR
Question 3 Explanation:
The Correct Answer Among All the Options is D

By rearranging the circuit,

Truth table:

The functionality of the above circuit is XNOR

 Question 4
A standard CMOS inverter is designed with equal rise and fall times (βn = βp). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin NMH?
 A N ML increases and N MH decreases. B Both N ML and N MH increase. C N ML decreases and N MH increase. D No change in the noise margins.
Question 4 Explanation:
 Question 5
The state transition diagram for the circuit shown is

 A B C D
Question 5 Explanation:
 Question 6
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = ‘0’. If the input condition is changed simultaneously to P = Q = ‘1’, the outputs X and Y are
 A X = ‘1’, Y = ‘1’ B either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’ C either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’ D X = ‘0’, Y = ‘0’
Question 6 Explanation:
 Question 7
The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is
 A 1 B 6 C 7 D 8
Question 7 Explanation:
 Question 8
The circuit is formed as shown below. The output S and C implement
 A Two bit adder with sum and carry respectively B Two bit subtractor with sum and borrow respectively C D None of the above
Question 8 Explanation:
From the diagram
carry (C) can be written as: B

sum (S) can be written as:
S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A
B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)
 Question 9
The circuit is formed as shown below. The output S and C implement
 A Two bit adder with sum and carry respectively B Two bit subtractor with sum and borrow respectively C D None of the above
Question 9 Explanation:
From the diagram
carry (C) can be written as: B

sum (S) can be written as:
S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A
B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)
 Question 10
What is the value of the register formed from D flip-flops using Q0, Q1 and Q2 as output (Q0 Q1Q2) after 14 cycles
 A 110 B 000 C 001 D 011
Question 10 Explanation:
This is a very interesting question and we can get answer quickly if we use smart way to solve it. The circuit is called a Switchtail counter or Johnson counter . An N-bit Johnson counter has 2N states and it recycles after 2N clocks. The given counter has 3 bits, so it recycles after 6 clocks. The initial state is not given, so let us assume it to be 000. After 12 clocks it will return to 000. After thirteenth clock it will be 100. After fourteenth clock it will be 110.
Hence Option(A) is the correct answer.
 Question 11
A 4-bit shift register circuit configured for right-shift operation, , is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.
 A Fill in the Blank Type Question
Question 11 Explanation:
 Question 12

The following FIVE instructions were executed on an 8085 microprocessor.
MVI A, 33H
MVI B, 78H
CMA
ANI 32H
The Accumulator value immediately after the execution of the fifth instruction is

 A 00H B 10H C 11H D 32H
Question 12 Explanation:
 Question 13
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB =00,01,10 and 11. Assume that X1N is is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state QAQB=00 and clocked, after a few clock cycles, it starts cycling through
 A all of the four possible states if X1N=1 B three of the four possible states if X1N=0 C only two of the four possible states if X1N=1 D Only two of the four possible states if XIN=0
Question 13 Explanation:
 Question 14
The logic realized by the given circuit is
 A NOR B AND C NAND D XOR
Question 14 Explanation:
 Question 15
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is____________.
 A Fill in the Blank Type Question
Question 15 Explanation:
According to the given data,
Green is turned ON for 70 seconds
Yellow is turned ON for 5 seconds
Red is turned ON for 75 seconds
Total time to complete one cycle for all 3 lights = (70 + 5 +75) seconds = 150 seconds
Time period of available clock = 5 seconds
Total number of unique states required

Minimum number of flip-flops required is,

flip flops are required for the stable output to make transition error zero and false triggering of output.

 Question 16
The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.

The number of distinct values of (out of the 16 possible values) that given is __________.

 A Fill in the Blank Type Question
Question 16 Explanation:

Number of distinct values of X3 X2 X1 X0 (out of the 16 possible values)
that give Y = 1 is 8.
 Question 17
A 2 * 2 ROM array is built with the help of diodes as shown in the circuit below. Here and are signals that select the word lines and and are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the road operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to (where or 1 and or 1) stored in the ROM?
 A B C D
Question 17 Explanation:

The following can be observed,
When otherwise
When otherwise
So, and

Hence,
 Question 18
A four-variable Boolean function is realized using multiplexers as shown in the figure.

The minimized expression for is
 A B C D
Question 18 Explanation:
 Question 19
In a DRAM,
 A periodic refreshing is not required B information is stored in a capacitor C information is stored in a latch D both read and write operations can be performed simultaneously
Question 19 Explanation:
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

Soure : https://en.wikipedia.org/wiki/Dynamic_random-access_memory
 Question 20
Consider the circuit shown in the figure.

The Boolean expression F implemented by the circuit is
 A B C D
Question 20 Explanation:
 Question 21
In a DRAM,
 A periodic refreshing is not required B information is stored in a capacitor C information is stored in a latch D both read and write operations can be performed simultaneously
Question 21 Explanation:
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

Soure : https://en.wikipedia.org/wiki/Dynamic_random-access_memory
 Question 22
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input „In‟ and an output ‘Out’. The initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.
 A Fill in the Blank Type Question
Question 22 Explanation:
From the state diagram, let us obtain the transition of states and out when IN channel.
Initial state is
So, the input sea is 10101101001101 Hence the number of times ‘Out’ will be 1 is 4.
 Question 23
Identify the circuit below.
 A Binary to Gray code converter B Binary to XS3 converter C Gray to Binary converter D None of the above
Question 23 Explanation:
As we know in a decoder w.r.t any binary input combination the corresponding output pin is high and remaining low.
Similarly to the encoder one input is high among all and its equivalent binary combination is available at output.
In this case to identify the functionality, let give some arbitrary binary input and observe the output.
Let [X2 X1 X0] is [1 0 1] respectively then OP5  = IP7 Then [Y2 Y1 Y0] is [1 1 1]
If [X2 X1 X0] is [1 1 1] then [OP7 = IP5 ] so [Y2 Y1 Y0= 101] [X2 X1 X0] is [1 0 0] then [OP4 = IP6 = 1] so [Y2 Y1 Y0= 110]
From the above we can say that
If input 101 then output is 111
111 101
So input binary and output gray.
 Question 24
The functionality implemented by the circuit below is
 A 2-to-1 multiplexer B 4-to-1 multiplexer C 7-to-1 multiplexer D 6-to-1 multiplexer
Question 24 Explanation:
 Question 25
In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?
 A for POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction has to be reversed. B Memory write operations are slower than memory read operations in an 8085 based system. C The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer. D Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
Question 25 Explanation:
In push operation 3 cycles involved: 6T+3T+3T = 127
POP operation 3 cycles involved: 4T+3T+3T = 107
So in the opcode fetch cycle 2T states are extra in case of push compared to POP and this is needed to decrement the SP.
 Question 26
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively
 A B and F B A and F C H and F D A and C
Question 26 Explanation:
In an 8085 microprocessor, after performing the addition, result is stored in accumulator and if any carry (overflow bit) is generated it updates flags.
The shift registers A and F store the result of an addition and the overflow bit.
 Question 27
A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is __________ .
 A Fill in the Blank Type Question
Question 27 Explanation:
 Question 28
Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts) corresponding to the digital signal 1111 is ________.
 A Fill in the Blank Type Question
Question 28 Explanation:
 Question 29
The Boolean expression converted into the canonical product of sum (POS) form is
 A B C D
Question 29 Explanation:
 Question 30
All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip (i.e., A = C = 1 and B = 0) and remain in that state. For t > 0, output Z = 1 for a duration (in ns) of _________.
 A Fill in the Blank Type Question
Question 30 Explanation:
 Question 31
A 3-input majority gate is defined by the logic function M(a, b,c) = ab + be + ca . Which one of the following gates is represented by the function ?
 A 3-input NAND gate B 3-input XOR gate C 3-input NOR gate D 3-input XNOR gate
Question 31 Explanation:
The Correct Answer Among All the Options is B

 Question 32
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor and the supply voltage is 5V. The D flip-flops D1, D2, D3, D4 and D5, are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle. The average power dissipated (in mW) in the resistor R is_____
 A Fill in the Blank Type Question
Question 32 Explanation:

 Question 33
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the select bits with A being the more significant select bit. Which one of the following statements correctly describes the choice of signals to be connected to the inputs I0, I1, c and I3 so that the output is Cout?
 A I0=0, I1=Cin, I2= Cin and I3 =1 B I0=1, I1= Cin, I2 = Cin and I3 =1 C I0 =0, I1=0, I2 =1 and I3 = Cin D I0=0, I1 = Cin, I2 =1 and I3 = Cin,
Question 33 Explanation:
Truth Table for the above circuit
 Question 34
An 8 Kbyte ROM with an active low Chip Select input is to be used in an 8085-microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH.
The address lines are designated as A15 to A0, where A 15is the most significant address
bit. Which one of the following logic expressions will generate the correct signal for this ROM?
 A B C D
Question 34 Explanation:
Address varying from 1000 H to 2FFFH
i.e.
0001 0000 0000 0000 H
.
.
.
0010 1111 1111 1111 H

Thus
 Question 35
In an N bit flash ADC, the analog voltage is fed simultaneously to 2N— 1 comparator. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source Vin (whose output is being converted to digital format) has a source resistance of 75 ohms as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full-scale input change for proper conversion. Assume that the time taken by the thermometer to the binary encoder is negligible. If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate?
 A 1 mega samples per second B 6 mega samples per second C 64 mega samples per second D 256 mega samples per second
Question 35 Explanation:
 Question 36
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure. Which one of the following statements is correct?
 A Transitions from State A are ambiguously defined. B Transitions from State B are ambiguously defined. C Transitions from State C are ambiguously defined. D All of the state transitions are defined unambiguously.
Question 36 Explanation:
 Question 37
In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be
 A 4E and 0 B 4E and 1 C 4F and 0 D 4F and 1
Question 37 Explanation:
 Question 38
The logic functionality realized by the circuit shown below is
 A OR B XOR C NAND D AND
Question 38 Explanation:
All the transistor are NMOS. We know when input to gate is 0, NMOS behave as open circuit. If input to Gate is 1, NMOS is short circuit.
We can redraw the circuit as
 Question 39
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
 A 4 B 5 C 6 D 7
Question 39 Explanation:

 Question 40
Following is the K-map of a Boolean function of five variables P, Q, R, S and X. The minimum sum-of-product (SOP) expression for the function is

 A B C D
Question 40 Explanation:
 Question 41
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is_______.
 A Fill in the Blank Type Question
Question 41 Explanation:
Case (i) When T = 0
Ttotal = NOR Gate Delay + 1st MUX Delay + 2nd MUX Delay
= 2+1.5+1.5 = 5ns
Case (ii) When T = 1
Ttotal = 1st NOT-Gate Delay + 1st MUX Delay + 2nd NOR-Gate Delay + 2nd MUX Delay
= 1+1.5+2+1.5 = 6 ns
So, the maximum delay = 6 ns.
 Question 42
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero. If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
 A mod-5 counter B mod-6 counter C Mod-7 counter D mod-8 counter
Question 42 Explanation:
 Question 43
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset . The counter corresponding to this circuit is
 A a modulo-5 binary up counter B a modulo-6 binary down counter C a modulo-5 binary down counter D a modulo-6 binary up counter
Question 43 Explanation:
Since 1 0 1 -> state becomes 0 0 0
so it is MOD–5 counter (UP)

From the figure, it can be seen it is basic modulo UP counter configuration because clock is negative edge triggering.
At Modulo-5
1 0 1
For this state, all the 3 flip flops will be set to initial condition.
the states will be= 000,001,010,011,100 at 101 it will reset to 000
 Question 44
In the circuit shown diodes D1, D2 and D3 are ideal, an the inputs E1, E2 and E3 are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?
 A 3-input OR gate B 3-input NOR gate C 3-input AND gate D 3-input XOR gate
Question 44 Explanation:
The Correct Answer Among All the Options is C
Correct option is (C).
If any of the inputs from E1, E2, E3 is logic 0 (means 0V) then the corresponding diode will be ‘‘ON’’ resulting in 0V at the output and only when all the inputs are logic 1 (means VDD) then V0 (output voltage) will be high, hence, resulting into 3 input AND-gate. Truth table for the logic circuit is shown below.
 Question 45
Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in register B and C?
 A B C D
Question 45 Explanation:
LOOP ADD C (adding the contents of C to accumulator and store it to accumulator)
DCR B (Decrementing the content of registers B)
JNZ LOOP
HLT
Hence, decreasing the number in B as many-time as adding the another number C will result in product of two numbers till value in registers B is zero.
The codes given in option(C), executes the above instructions
 Question 46
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1Y0 is set to 111. The value of output Y after three clock cycles is
 A 000 B 001 C 010 D 100
Question 46 Explanation:
 Question 47
A universal logic gate can implement nay Boolean function by connecting sufficient number of them appropriately. Three gates are shown.

Which one of the following statements is TRUE?
 A Gate 1 is a universal gate B Gate 2 is a universal gate C Gate 3 is a universal gate D None of the gates shown is a universal gate
Question 47 Explanation:
For a universal gate, it consist of one basic gate (AND, OR) and inverter (NOT gate).
If we put Y=0 then Gate-3 is behaving like an Inverter and once inverter can be designed by this gate then It is easy to design AND & OR gate by this.
Gate (1) and Gate (2) don’t have inverter.
Hence Gate (3) is a universal gate.
 Question 48
An SR latch is implemented using TTL gates as shown in the figure. The set and rest pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing
 A NOR gates to NAND gates B Inverters to buffers C NOR gates no NAND gates and inverters to buffers D 5 V to ground
Question 48 Explanation:
SR latch truth table is given below.

This truth table can be obtained from the given circuit, if we change 5 V to ground.
The desired operation can be achieved by changing 5V to GND
 Question 49
In the figure shown, the output Y is required to be Y = AB + . The gates G1 and G2 must be, respectively,
 A NOR, OR B OR, NAND C NAND, OR D AND, NAND
Question 49 Explanation:
 Question 50
In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?
 A MOV B, M B PCHL C RNZ D SBI BEH
Question 50 Explanation:
Generally arithmetic or logical instructions update the data of accumulator and flags. So, in the given option only SBI BEH is arithmetic instruction.
SBI BEH: Add the content of accumulator with immediate data BE H and store the result in accumulator.
Hence, the correct option is (D).
 Question 51
The figure shows a binary counter with synchronous clear input. With the decoding log shown, the counter works as a
 A mod-2 counter B mod-4 counter C mod-5 counter D mod-6 counter
Question 51 Explanation:
 Question 52
A function of Boolean variables X, Y and Z is expressed in terms of the min-terms as
F(X, Y, Z) =
Σ(1, 2, 5, 6, 7)

Which one of the product of sums given below is equal to the function F(X, Y, Z)?
 A B C D
Question 52 Explanation:
 Question 53
The Boolean expression simplifies to
 A X B Y C XY D X + Y
Question 53 Explanation:
 Question 54
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is __________
 A 52.5 B 54.5 C 62.5 D 64.5
Question 54 Explanation:
We observed that the Given circuit is a Ripple counter or Asynchrnous counter. In Ripple counter, o/p frequency of each flip-flop is half of the input frequency if their all the states are used otherwise o/p frequency of the counter is
So, the frequency at
 Question 55
The output F in the digital logic circuit shown in the figure is
 A B C D
Question 55 Explanation:
 Question 56
Which one of the following is the complete set of essential prime implicants ?
 A A B B C C D D
Question 56 Explanation:
Essential prime implicants
• Essential prime implicants are those which contains atleast one element which is not in any other
• Number of prime implicants in which any of “1” is one time paired, is called Essential Prime Implicants
 Question 57
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?
 A Input A is connected to B Input A is connected to C Input A is connected to and S is complemented D Input A is connected to
Question 57 Explanation:
 Question 58
For an n-variable Boolean function, the maximum number of prime implicants is
 A B C D
Question 58 Explanation:
For an n-variable Boolean function, the maximum number of prime implicants = 2(n-1)
 Question 59
The number of bytes required to represent the decimal number 1856357 in packed BCD(Binary Coded Decimal) form is __________ .
 A 1 B 2 C 3 D 4
Question 59 Explanation:
In packed BCD (Binary Coded Decimal) typically encoded two decimal digits within a single byte by taking advantage of the fact that four bits are enough to represent the range 0 to 9. So, 1856357 is required 4-bytes to stored these BCD digits
 Question 60
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by
 A B C D
Question 60 Explanation:
 Question 61
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4
 A W1 B W2 C W3 D W4
Question 61 Explanation:

Explanation-2
This circuit has used negative edge triggered, so output of the D-flip flop will changed only when CLK signal is going from HIGH to LOW (1 to 0)

This is a synchronous circuit, so both the flip flops will trigger at the same time and will respond on falling edge of the Clock. So, the correct output (Y) waveform is associated to w3 waveform.
 Question 62
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0,0. The sequence generated at Q1 upon application of clock signal is
 A 01110… B 01010… C 00110… D 01100…
Question 62 Explanation:

So, the output sequence generated at Q1 is 01100….
 Question 63
For the 8085 microprocessors, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is
 A MVI A, F8H B IN F8H C OUT F8H D LDA F8F8H
Question 63 Explanation:
This circuit diagram indicating that it is memory mapped I/O because to enable the 3-to-8 decoderis required active low signal through is required active low through it means I/o device read the status of device LDA instruction is appropriate with device address.
Again to enable the decoder o/p of AND gate must be 1 and signal required is 1 which is the o/p of multi-i/p AND gate to enable I/O device.
So,

The correct instruction used LDA F8F8H
 Question 64
The circuit shown in the figure is a
 A Toggle Flip Flop B JK Flip Flop C SR Latch D Master-Slave D Flip Flop
Question 64 Explanation:
1. Master-Slave D Flip Flop because clock input to both Flip Flops are complement of each other
2. Another point is Given circuit diagram is a master slave D flip flop in which master flip-flop works on positive cycle of clock and slave flip-flop works on negative cycle of clock.
3. Latches are used to construct Flip-Flop. Latches are level triggered, so if you use two latches in cascaded with inverted clock, then one latch will behave as master and another latch which is having inverted clock will be used as a slave and combined it will behave as a flip-flop. So given circuit is implementing Master-Slave D flip-flop
 Question 65
Consider the multiplexer based logic circuit shown in the figure.

Which one of the following Boolean functions is realized by the circuit?
 A B C D
Question 65 Explanation:
 Question 66
In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by
 A B C D
Question 66 Explanation:
 Question 67
In the circuit shown in the figure, if C=0, the expression for Y is
 A B C D
Question 67 Explanation:
 Question 68
The output (Y) of the circuit shown in the figure is
 A B C D
Question 68 Explanation:

This circuit is CMOS implementation
If the NMOS is connected in series, then the output expression is product of each input with
complement to the final product.
 Question 69
An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by
 A B C D
Question 69 Explanation:
 Question 70
A 16-bit ripple Carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.
 A 170 B 175 C 185 D 195
Question 70 Explanation:
Consider the last full adder for worst case delay.
Time after which output carry bit becomes available from the last full adder
= Total number of full adders X Carry propagation delay of full adder
= 16 x 12 ns
= 192 ns

Time after which output sum bit becomes available from the last full adder
= Time taken for its carry in to become available + Sum propagation delay of full adder
= { Total number of full adders before last full adder X Carry propagation delay of full adder } + Sum propagation delay of full adder
= { 15 x 12 ns } + 15 ns
= 195 ns
 Question 71
An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A15 - A8 is
 A 1FH, 1FH, 20H, 12H B 1FH, FEH, 1FH, FFH, 12H C 1FH, 1FH, 12H, 12H D 1FH, 1FH, 12H, 20H, 12H
Question 71 Explanation:
 Question 72
A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles
 A an AND gate B an OR gate C an XOR gate D a NAND gate
Question 72 Explanation:
The purpose of staircase wiring is, one should be able to switch on and switch off lights from more than one point and these can be achieved by 2-way switches.The position of switches A, B and the condition of the lamp can be tabulated as below.

(i.e)  lamp glows when  switch A & B positions are different.
This truth table simply resembles the logic of a XOR gate as shown below

Form the truth table we can say that XOR logic is implemented
 Question 73
For 8085 microprocessor, the following program is executed
MVI A, 05 H;
MVI B, 05H;
DCR B;
JNZ PTR;
HLT;
At the end of program, accumulator contains
 A 17 H B 20H C 23H D 05H
Question 73 Explanation:
 Question 74
In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If is X and Y are digital signals with 0 V as logic 0 and as logic 1, the Boolean expansion for Z is
 A XY B C D
Question 74 Explanation:
 Question 75
There are four chips each of 1024 bytes connected to a 16 bit address bus address bus as shown in the figure below. RAMs, 1, 2, 3, and 4 respectively are mapped to addresses
 A 0C00H–0FFFH. 1C00H-1FFFH. 2C00H-2FFFH, 3C00H-3FFFH B 1800H-1FFFH. 2800H-2FFFH. 3800H-3FFFH. 4800H-4FFFH C 0500H-08FFH, 1500H-18FFH. 3500H-38FFH. 5500H-58FFH D 0800H-0BFFH. 1800H-1BFFH. 2800H-2BFFH. 3800H-3BFFH
Question 75 Explanation:
 Question 76
Consider the given circuit

In this circuit, the race around
 A Does not occur B Occurs when CLK = 0 C Occurs when CLK = 1 and A = B = 1 D Occurs when CLK = 1 and A = B = 0
Question 76 Explanation:
 Question 77
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is
 A 4 B 6 C 8 D 10
Question 77 Explanation:
Output will be 1 if A > B.

• If B = 00 then there will be three combinations for which OIP will be 1 i.e. when A = 01, 10, or 11.
• If B = 01 there will be two conditions i.e. A = 10 and 11.
• If B = 10 there will be one condition i.e. A = 11.
So total 6 combinations are there for which O/P will be 1.
 Question 78
In the circuit shown
 A B C D
Question 78 Explanation:
Series combination of n-mos is equivalent to AND and parallel combination is equivalent to OR.
So,

 Question 79
In the sum of products function f(X, Y, Z) = ∑(2, 3, 4, 5), the prime implicants are
 A B C D
Question 79 Explanation:
The Karnaugh Map of the given function is shown below

So prime implicants are and .
 Question 80
The state transition diagram for the logic circuit shown is
 A B C D
Question 80 Explanation:
 Question 81
The circuit is formed as shown below. The output S and C implement
 A Two bit adder with sum and carry respectively B Two bit subtractor with sum and borrow respectively C D None of the above
Question 81 Explanation:
The Correct Answer Among All the Options is B
Look at the diagram carefully. Here clearly, carry (C) can be written as:
B
And sum (S) can be written as:
S= A + = A
So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= AB and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)
Refer the Topic Wise Question for Application of Logic Gates Digital Circuits
 Question 82
What is the value of the register formed from D flip-flops using Q0, Q1 and Q2 as output (Q0 Q1Q2) after 14 cycles
 A 110 B 000 C 001 D 011
Question 82 Explanation:
The Correct Answer Among All the Options is A
Given: A register formed by D flip flops. Here, we have to find the values of the output terminals after 14 cycles.
For determining this, we have to recall all the counter types. See this one is actually johnson counter(Inverted output of the last flip flop is connected to the input of the first flip flop). So, this is a 3 input johnson counter, which means there will be 6 unique states of this counter.
1st Reset is applied and all outputs=000
Next Q0=1 , Q1=0 and Q2=0
Next Q0=1 , Q1=1 and Q2=0
So, like this it will be continued, and on 13th cycle, output states will be:
Q0=1 , Q1=0 and Q2=0
And 14th Cycle: Q0=1 , Q1=1 and Q2=0
Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits
 Question 83
The output voltage from a 5-bit ladder type DAC that has a digital input of 11010, and by assuming 0 = 0 V and 1 = + 10V, is nearly
 A 26.0 V B 16.3 V C 10.3 V D 8.1 V
Question 83 Explanation:
(11010)2 = (26)10
VDAC = resolution x (decimal equivalents)

VDAC = 8.1 V
 Question 84
An 8-bit D/A converter has step size of 20 mV. The full-scale output and the resolution will be nearly
 A 5.1 V and 0.3% B 4.6 V and 0.4% C 5.1 V and 0.4% D 4.6 V and 0.3%
Question 84 Explanation:
Full scale output
Resolution = step size = 20 mV
VFS = (28–1) × resolution
= 255 × 20 mV
VFS = 5.1V

Resolution
% resolution =

% resolution = 0.4%
 Question 85
Consider the following expression:

The simplification of this by using theorems of Boolean algebra will be
 A A + B B A ⨁ B C (A + B) (A . B) D A . B
Question 85 Explanation:
 Question 86
An electric power generating station supplies power to three loads A, B and C. Only a single generator is required when any one load is switched on. When more than one load is on, an auxiliary generator must be started. The Boolean equation for the control of switching of the auxiliary generator will be
 A AA + BB + CC B ABC + BCA + CAB C AB + AC D AB + AC + BC
Question 86 Explanation:

F = BC + AC + AB + ABC
∴ F = AB + BC + AC
 Question 87
Which one of the following types of instructions will be used to copy from the source to the destination location?
 A Arithmetic instruction B Data transfer instructions C Logical instructions D Machine control instructions
Question 87 Explanation:
Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group −

### Instruction to transfer a word

• MOV − Used to copy the byte or word from the provided source to the provided destination.
• PPUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.

### Instructions for input and output port transfer

• IN − Used to read a byte or word from the provided port to the accumulator.
• OUT − Used to send out a byte or word from the accumulator to the provided port.

### Instructions to transfer the address

• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.

### Instructions to transfer flag registers

• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
• PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag register.
 Question 88
A cascaded arrangement of flip-flops, where the output of one flip-flop drives the clock input of the following flip-flop, is known as
 A synchronous counter B ripple counter C ring counter D up counter
Question 88 Explanation:
 Question 89
The number of flip-flops required to construct an 8-bit shift register will be
 A 32 B 16 C 8 D 4
Question 89 Explanation:
An ‘n’ bit shift register needs ‘n’ number of flip flops.
So, the 8 bit shift register needs ‘8’ number of flip flops.

Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.

Shift registers are basically of 4 types. These are:
Serial In Serial Out shift register
Serial In parallel Out shift register
Parallel In Serial Out shift register
Parallel In parallel Out shift register

Note : Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to store n bits of data. A Register is a device which is used to store such information. It is a group of flip flops connected in series used to store multiple bits of data. The information stored within these registers can be transferred with the help of shift registers
 Question 90
Add 8 and 9 in BCD code
 A 00010111 B 00010001 C 01110111 D 10001001
Question 90 Explanation:
(8)101000
(9)10 1001
6 is added due to carry generated
∴(8)10 + (9)10 = (17)10
∴(17)10 = [0001 0111]BCD

Theory

BCD or Binary Coded Decimal is that number system or code which represents the 10 decimal digits in terms of binary numbers.

The following is table for Decimal number and it’s Binary Equivalent:

As seen above, when the Decimal equivalent exceeds 9, then we start writing the BCD equivalent as two Binary equivalents.

Now let’s have a look at some examples:

0101 + 0011 = 1000 (Binary addition). [If you compare this with the above table, you’ll find that 0101 is 5; 0011 is 3 and 1000 is 8.] We can do the same for every number whose sum comes to less than or equal to 9.

But if the addition is greater than 9,then what!

Simple! Let’s take an example:

0101 + 1000 = 1101 . [From table, 0101 is 5; 1000 is 8 and 1101 is 13.]

But the BCD equivalent of 13 is 0001 0011.

So we take the Binary addition obtained i.e 1101 and add 0110 (decimal 6) to it.

The result obtained is 1101 + 0110 = 1 0011 where the last 4 bits 0011 represent 3 and 1(can also be written as 0001, which means 1 in decimal equivalent). Thus we obtain 0001 0011 as final answer!

Thus, for any addition greater than 9, add binary equivalent of 6 to the Binary sum obtained and you’ll get it’s BCD equivalent.

Hope it helps. 🙂

Credits : Shukriya!

 Question 91
Convert the binary number 11000110 to Gray code
 A 001000101 B 10100100 C 11100110 D 10100101
Question 91 Explanation:
Gray code = 10100101

Gray to Binary Code Converter

From the above operation, finally we can get the binary values like
b3 = g3,
b2 = b3 XOR g2,
b1= b2 XOR g1,
b0 = b1 XOR g0.
 Question 92
The decimal value of the signed binary number 10101010 expressed in 2’s complement will be
 A -42 B -86 C -116 D -170
Question 92 Explanation:
 Question 93
The finite state machine in which
1) the output is a function of the current state and inputs
2) the output is a function of only the current state
Which of the following machines are respectively correct for these styles?
 A Mealy machine and Moore machine B Moore machine and Mealy machine C State machine and Mealy machine D State machine and State machine
Question 93 Explanation:
Mealy Machine Moore Machine
Output depends both upon the present state and the present input Output depends only upon the present state.
Generally, it has fewer states than Moore Machine. Generally, it has more states than Mealy Machine.
The value of the output function is a function of the transitions and the changes, when the input logic on the present state is done. The value of the output function is a function of the current state and the changes at the clock edges, whenever state changes occur.
Mealy machines react faster to inputs. They generally react in the same clock cycle. In Moore machines, more logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later.
 Question 94
A controller that takes control of the buses and transfers data directly between source and destination bypassing the microprocessor is known as
 A DMA controller B read-write controller C high-speed controller D master-slave controller
Question 94 Explanation:
Direct Memory Access:
The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit
 Question 95
A 2-byte instruction which accepts the data from the input port specified in the second byte and loads into the accumulator is
Question 95 Explanation:
IN (8-bit port address) 1 byte is for opcode and 1 byte for 8 bit port address so it is a 2 Byte instruction and this instruction is used to accept the data from the inport port and load this data into accumulator.
 Question 96
Consider the following instruction:
El
MVl A, 08H
SlM
It means
 A disable all interrupts B enable all interrupts C disable RST 7.5 and 6.5 D enable RST 7.5 and 6.5
Question 96 Explanation:
EI means enable all maskable interrupts
MVI A, 08H load accumulator with 08H
Data of A is copied to 5IM
A has (0000 1000)2
 Question 97
The instruction BC 0X15 means
 A jump 15 bytes relative to the program counter B copy and load 15 words in reverse direction to the program counter C move to a location by 15 bits to the program counter D redirect (jump) to a location by 15 words relative to the program counter
Question 97 Explanation:
Micro processor does not have any instruction such as BC so it is a printing mistake
It should be JC OX 15 which means jump by 15 bytes if carry is zero relative to program counter.
 Question 98
Which of the following constraints are to be considered by the designer while designing an embedded system?
1) Selecting the microcontroller as a controlling device
2) Selecting the language to write the software
3) Partitioning the tasks between hardware and software to optimize the cost
Select the correct answer using the code given below
 A 1, 2 and 3 B 1 and 2 only C 1 and 3 only D 2 and 3 only
Question 98 Explanation:
Following constraints are to be considered by the designer while designing an embedded system :
• Microcontroller is selected as controlling device
• Language is selected to write the program (software) without difficulties.
• Partioning the tasks between hardware and software to optimize the case.
 Question 99
The following six (6) items consist of two statements, one labelled as ‘Statement (I)’ and the other as ‘Statement (II)‘. You are to examine these two statements carefully and select the answers to these items using the code given below:
Statement (I): Sign-magnitude representation is rarely used in implementing the integer of the ALU.
Statement (II): There are two representations of zero in sign-magnitude representation.
 A Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I) B Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I) C Statement (I) is true but Statement (II) is false D Statement (I) is false but Statement (II) is true
Question 99 Explanation:
In modern computer system 2’s complement representation is used.
1) In sign magnitude form and 1’s complement form, the disadvantage is ‘0’ has two representations.
2) Only 2’s complement form has unique representation of 0. Hence 2’s complement form is preferred.

In sign-magnitude format, MSB decides the sign. If MSB is 0 then sign is positive and if MSB is 1, then sign is negative (i.e. number is negative)
e.g. For 3 bit sign magnitude representation
000 -> +0
100 -> -0
Hence statement (II) is correct explanation of statement (I).

1. Signed Magnitude Method :
In the signed magnitude method number is divided into two parts: Sign bit and magnitude. Sign bit is 1 for negative number and 0 for positive number. Magnitude of number is represented with the binary form of the number.

2. 2’s Complement Method :
In 2’s complement method, positive numbers are represented in the same way as they are represented in sign magnitude method. But if the number is negative, first represent the number with positive sign and then take 2’s complement of that number.

Difference between Signed Magnitude and 2’s Complement Method :
SIGNED MAGNITUDE METHOD 2’S COMPLEMENT METHOD
It is a method to denote fixed point signed numbers. It is also used to denote fixed point signed numbers.
Number is divided into two parts. Number is considered as a whole.
Sign bit is considered explicitly. Sign bit is not considered explicitly.
Additional hardware is required for resultant sign of arithmetic. No additional hardware is required in 2’s complement method.
Addition and subtraction are performed on separate hardware. Addition and subtraction are performed by using adder only.
It has two different representation for 0. One is +0 and second is -0. (+0 : 0000 0000) & (-0 : 1000 0000) 0 has only one representation for -0 and +0 (+0 or -0 : 0000 0000).
It is non-weighted system. It assigns negative weight to the sign bit.
 Question 100
Difference in dynamic range of 32-bit binary number (B) and floating point number(F) is? StANDARD Format for B and F as given below:
B =
 A 6.02(27-30) dB B 6.02(28-31) dB C 6.02(27-31) dB D 6.02(28-30) dB
Question 100 Explanation:
The Correct Answer Among All the Options is B
Dynamic range =
Therefore , for 32-bit binary number (B),
dynamic range = 31(6.02)dB
for floating point number (F) ,
dynamic range= (6.02)dB
now , required difference is = 31(6.02)dB - (6.02)dB
= 6.03()
Refer the Topic Wise Question for Number Systems Digital Circuits
 Question 101

If Sys clock frequncy is > 4 * clk_ext frequency. What is the functionality of above circuit?
 A Falling Edge detector with Pulse width of Qout = one cycle of Sys clk B Rising Edge detector with Pulse width of Qout = one cycle of Sys clk C Falling Edge detector with Pulse width of Qout = one cycle of clk_ext D Rising Edge detector with Pulse width of Qout = one cycle of clk_ext
Question 101 Explanation:
The Correct Answer Among All the Options is B
D flip-flop is level triggered.
Sys clock frequncy is > 4 * clk_ext frequency.
It will detect the rising edge of clock external input , but with a delay of seconds and width of pulse =.
Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits
 Question 102
Simplify the Boolean expression F(w,x,y,z) =
 A w+x+y+z B y’ + w’z’+xz’ C y +w’z’+xz D x+z’w’y+x’
Question 102 Explanation:
The Correct Answer Among All the Options is B
k-map for given boolean exoression:

F(w,x,y,z)= +
=
Refer the Topic Wise Question for Minimization Digital Circuits
 Question 103
High State noise margin of standard TTL and 5V CMOS logic gate are
 A 0.4V, 0.4V B 0.4V, 1V C 1V, 0.4V D 1V, 1V
Question 103 Explanation:
The Correct Answer Among All the Options is B
in a digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.
Refer the Topic Wise Question for Logic Families Digital Circuits
 Question 104
VHDL
entity test is
port
(
data : in std_logic;
clk : in std_logic;
rset : in std_logic;
q : out std_logic
);
end test;
architcture behav of test is
begin
process (clk)
begin
if (clk’event and clk =’1’) then
if (reset =’0’) then
q <= ‘0’;
else
q <= data;
end if;
end if;
end process;
end behav;
VERILOG
module test (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always @ (posedge clk)
if (reset)
q = 1’b0;
else q = data;
endmodule
The Above Verilog/VHDL module depicts which sequential element:
 A Rising edge Flip-flop with synchrounus Reset B Falling edge Flip-flop with synchrounus Reset C Rising edge Flip-flop with asynchrounus Reset D Falling edge Flip-flop with asynchrounus Reset
Question 104 Explanation:
The Correct Answer Among All the Options is A
in the given programming , ‘if’ condition is used to check occurrence of rising edge . and as RESET is used with every clock cycle that indicates it is synchronous.
Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 105
What is the content of Accumulator in binary after execution of following 8051 Assembly code :
MOV A, #27h
MOV R1, A
SWAP A
ANLA, # OFH
MOV B, #10
MULAB
MOV R2, A
MOV A, #R1
ANL A, #0FH
 A 00011011 B 01110010 C 01010101 D 11001011
Question 105 Explanation:
The Correct Answer Among All the Options is A

Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 106
In a 16-Bit micro-controller if a two-dimensional integer array A[5][7] is stored at base location 0x8000, What is the address of A[4][2]?
 A 0x800C B 0x803C C 0x801F D 0x840
Question 106 Explanation:
The Correct Answer Among All the Options is B
microcontroller follows byte addressing storage method, even though it is 16-bit controller ,each address location stores only 1 bye.
Given 2’Dimensional array A[5][7] has total of 5 rows and 7 column. Array will be stored in memory by each row wise. Each row is having 7 elements , each of 2 bytes (16bits), which requires total of 14bytes(72).
= +(
=

Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 107
Content of variable flag after following ‘C’ code execution:
Unsigned char flag = 0x7C;
flag=flag | 0x80;
flag=flag | (1<<4);
flag&=~(1<<7);
flag^=(1<<6);
 A 0x1C B 0x20 C 0x24 D 0x3C
Question 107 Explanation:
The Correct Answer Among All the Options is D
Unsigned char flag = 0x7C;
flag=01111100
flag=flag | 0x80;
it is bitwise OR operation.

Flag =00111100=0x3C
Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 108
Process P1, P2 and P3 with execution time of 6 ms, 4 ms and 2 ms respectively enter in ready state together in order P1, P2, P3. Calculate the waiting and turnaround time of Process P1. Assuming no wait time due to I/O and round scheduling with time slot of 2 ms.
 A 6 ms, 12ms B 6 ms, 10 ms C 4 ms, 4 ms D 4 ms, 6 ms
Question 108 Explanation:
The Correct Answer Among All the Options is A
Round robin is a CPU scheduling algorithm where each process is assigned a fixed time slot in a cyclic way.
Turnaround time (TAT) is the time interval from the time of submission of a process to the time of the completion of the process. It can also be considered as the sum of the time periods spent waiting to get into memory or ready queue, execution on CPU and executing input/output
Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 109
A) HDL Coding /RTL Design
B) Synthesis
C) Static Timing Analysis
D) Place and Route
E) Programming file generation
What is the correct order of FPGA design flow?
 A A,B,C,D,E B A,B,D,C,E C B,D,C,E,A D C,A,D,E,B
Question 109 Explanation:
The Correct Answer Among All the Options is B

Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 110
Which of these is non-operational attribute of embedded system?
 A Response B Throughput C Security D Portability
Question 110 Explanation:
The Correct Answer Among All the Options is D
Operational Quality Attributes.:- These are attributes related to operation or functioning of an embedded system. The way an embedded system operates affects its overall quality. Some of the Operational Attributes are:
Response
Throughput
Reliability
Maintainability
Security
Safety
Non Operational Attributes :- These are attributes not related to operation or functioning of an embedded system. The way an embedded system operates affects its overall quality.These are the attributes that are associated with the embedded system before it can be put in operation. Some of non-operational attributes are :
Testability and Debug-ability
Evolvability
Portability
Time to prototype and market
Per unit and total cost
Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 111
For the below mentioned 8051 assembly code
Time elapse : MOV R0, #100
Part 1 : MOV R1, #50
Part 2 : MOV R2, #248
Part 3 : DJNZ R2, Part3
: DJNZ R1, Part2
: DJNZ R0, Part1
Assumptions:
Microcontroller is running at 12 MHz frequency and 1 machine cycle is having 12 clock cycles
MOV instruction takes 1 Machine cycle
DJNZ instruction takes 2 Machine cycle
Calculate time required for execution of Part 1
 A 2495600 B 2496300 C 2495300 D 2496600
Question 111 Explanation:
The Correct Answer Among All the Options is C
calculation of execution time for part-3:

1 machine cycle=12 = 12 =1

Code in part will be executed 248 times, so part3 execution time is
=248
DJNZ instruction takes 2 Machine cycle
=248
= 496
Code in part 2 will executed 50 times. So execution time for part 2 is
=50[1]
=50(499)
Code in part 1 will executed 100 times. So execution time for part 1 is
=100[1 +50(499)+2]
=2495300
Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 112
A) Program Counter (PC) Pushed to Stack
B) Generate LCALL to ISR
C) Complete Execution of instruction in progress
D) Clear the interrupt flag
E) Set interrupt in progress
Correct order of execution of action taken by 8051 micro-controllers when an interrupt occurs:
 A C,A,D,E,B B A,B,D,E,C C C,D,B,E,A, D A,C,B,D,E
Question 112 Explanation:
The Correct Answer Among All the Options is A
when an interrupt occurs:
(i) Microcontroller finishes the instruction it is executing.
(ii) Then it saves the address of next instructions (PC) on the stack.
(iii) It jumps to a fixed location in memory called the interrupt vector table that holds the address of the interrupt service routine.
(iv) Then it generates LCALL to ISR. After executing ISR, the microcontroller returns to the place where it was interrupted.
Refer the Topic Wise Question for Microprocessor Digital Circuits
 Question 113
Consider the output A and B with I0, I1, I2 and I3 as input
A=
B.
The above circuit is
 A 4:1 Multiplexer B De-Multiplexer C BCD circuit D Priority Encoder
Question 113 Explanation:
The Correct Answer Among All the Options is D
It is a priority encoder. A priority encoder(4 bit) is basically used to convert 4-bit input to equivalent binary representation. It takes in 4-bit as input, and has 2 bits at the output end. The truth table for a 4 x 2 priority encoder is generally given as:

Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits
 Question 114
In this truth table, all input combinations that are defined non explicitly (lower bits) are given as don't care(X). Also, see for the first row in output side don't care exist. It means that for input combination=0000, output doesn't exist.

The output Z
 A AB B ABC C ABC + AB D ABC +B
Question 114 Explanation:
The Correct Answer Among All the Options is B
First let us systematically approach for this, and determine Y1
So, Y1= C+ Next Y2=ABC, and finally Y3= A(
So, on reduction, Y3 can be written as: Y3=ABC
Now, Z= Y3+Y2=> ABC +ABC=> ABC
Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits
 Question 115
Consider the shift register

The frequency of signal x is fs and the shift register is clocked at the positive edge of 2fs. The time offset between A and B is
 A 1/(2fs) B 1/fs C 3/(2fs) D 1/(4fs)
Question 115 Explanation:
The Correct Answer Among All the Options is B
Here a shift register is given. We have to determine the time offset between A and B.
So, here it is given that the frequency of the signal if 2fs. 2fs frequency means time will be Ts/2(Ts being time).
So, now, So, Ts/2 is the first time. That is the time at which it has reached point A. We have to find time offset, which means that the time difference between A and B(when data reaches each point).
So, Ts/2 => Point A. Next 3Ts/2=> Point B. Similarly it will continue if other points are there. Now, Time offset= difference in time
So, difference in time between the two= 3Ts/2 -(Ts/2)=Ts. But in options only fs is given. Now we know that Ts=1/fs. So, answer will be option (b)
Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits
 Question 116
A High speed digital Subsystem requires three voltages V1, V2 and V3 with 1:2:1 power ratings respectively. The power supply is designed with the distribute power conversion scheme as shown in the following figure. What is the overall power conversion efficiency?
 A B C D
Question 116 Explanation:
The Correct Answer Among All the Options is A
We have to determine overall power conversion efficiency. Now, efficiency(ո) is generally given as: Vout/Vin
From the diagram it is clear that Vout= V1+2V2+V3(1+2+1=4V)
Now, we have to find out Vin. Since ո= Vout/Vin, so Vin= Vout/ո
Vout=4 V, and Vout=V1+2V2+V3=> V1(X)+V2(Y)+V3(Z)
So, Vin= X+(Y/ո2)+(Z/ո3)/ ո1
Replacing X by V, we get:
Vin=V(ո2ո3+2ո3+ո2)/ո2ո3ո1........ (a)
So, now substituting Vout=4 and Vin from (a), we will get option (a).
Refer the Topic Wise Question for Data Converters Digital Circuits
 Question 117
Which one of the following statement is not true for static random access memory (SRAM)
 A Static RAM stores data in the form of charge B They have low capacity, but offer high speed C It doesn't require periodic refreshing D They are made up of six transistor
Question 117 Explanation:
The Correct Answer Among All the Options is A
Static Random Access memory(SRAM) uses six transistors to store a single bit. SRAM retains data bits as long as there is power. SRAM doesn't have to be periodically refreshed. Only wrong option is option (a)
Refer the Topic Wise Question for Semiconductor Memories Digital Circuits
 Question 118
Following circuit implements a
 A De-Multiplexer B Multiplexer C Y= I0 (A0+ A1) D Y = I0 (+ A0)
Question 118 Explanation:
The Correct Answer Among All the Options is B
For answering this, we first have to find out the output expression, and then based on that expression, we can determine what circuit actually it is.
So, from the figure, we can write:
Y=A0I0+A1 => See this expression. It means that A0 will be on the output line whenever I0=1, and A1 will be on the output line whenever I0=0. So, totally two inputs and one select line. Clearly this is a 2 x 1 multiplexer circuit.
Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits
There are 118 questions to complete.