## Digital Circuits Subject Wise

Question 1 |

_{2}is __________ kHz.

Fill in the Blank Type Question |

Question 2 |

Hi-Z and D | |

Hi-Z and | |

0 and 1 | |

0 and D |

Question 3 |

XOR | |

SRAM Cell | |

Latch | |

XNOR |

By rearranging the circuit,

Truth table:

The functionality of the above circuit is XNOR

Question 4 |

_{n}= β

_{p}). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NM

_{L}) and the HIGH noise margin NM

_{H}?

N M _{L} increases and N M_{H} decreases. | |

Both N M _{L} and N M_{H} increase. | |

N M _{L} decreases and N M_{H} increase. | |

No change in the noise margins. |

Question 5 |

Question 6 |

X = ‘1’, Y = ‘1’ | |

either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’ | |

either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’ | |

X = ‘0’, Y = ‘0’ |

Question 7 |

1 | |

6 | |

7 | |

8 |

Question 8 |

Two bit adder with sum and carry respectively | |

Two bit subtractor with sum and borrow respectively | |

None of the above |

carry (C) can be written as: B

sum (S) can be written as:

S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A⊕B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)

Question 9 |

Two bit adder with sum and carry respectively | |

Two bit subtractor with sum and borrow respectively | |

None of the above |

carry (C) can be written as: B

sum (S) can be written as:

S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A⊕B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)

Question 10 |

_{0}, Q

_{1}and Q

_{2}as output (Q

_{0}Q

_{1}Q

_{2}) after 14 cycles

110 | |

000 | |

001 | |

011 |

Hence Option(A) is the correct answer.

Question 11 |

Fill in the Blank Type Question |

Question 12 |

The following FIVE instructions were executed on an 8085 microprocessor.

MVI A, 33H

MVI B, 78H

ADD B

CMA

ANI 32H

The Accumulator value immediately after the execution of the fifth instruction is

00H | |

10H | |

11H | |

32H |

Question 13 |

_{A}Q

_{B}=00,01,10 and 11. Assume that X

_{1N}is is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state Q

_{A}Q

_{B}=00 and clocked, after a few clock cycles, it starts cycling through

all of the four possible states if X _{1N}=1 | |

three of the four possible states if X _{1N}=0 | |

only two of the four possible states if X _{1N}=1 | |

Only two of the four possible states if X _{IN}=0 |

Question 14 |

NOR | |

AND | |

NAND | |

XOR |

Question 15 |

Fill in the Blank Type Question |

Green is turned ON for

**70 seconds**

Yellow is turned ON for

**5 seconds**

Red is turned ON for

**75 seconds**

Total time to complete one cycle for all 3 lights = (70 + 5 +75) seconds =

**150 seconds**

Time period of available clock =

**5 seconds**

Total number of unique states required

Minimum number of flip-flops required is,

flip flops are required for the stable output to make transition error zero and false triggering of output.

Question 16 |

The number of distinct values of (out of the 16 possible values) that given is __________.

Fill in the Blank Type Question |

Number of distinct values of X3 X2 X1 X0 (out of the 16 possible values)

that give Y = 1 is 8.

Question 17 |

**2 * 2**ROM array is built with the help of diodes as shown in the circuit below. Here and are signals that select the word lines and and are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the road operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to (where or 1 and or 1) stored in the ROM?

The following can be observed,

When otherwise

When otherwise

So, and

Hence,

Question 18 |

The minimized expression for is

Question 19 |

periodic refreshing is not required | |

information is stored in a capacitor | |

information is stored in a latch | |

both read and write operations can be performed simultaneously |

**Dynamic random-access memory (DRAM)**is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

Soure : https://en.wikipedia.org/wiki/Dynamic_random-access_memory

Question 20 |

The Boolean expression F implemented by the circuit is

Question 21 |

periodic refreshing is not required | |

information is stored in a capacitor | |

information is stored in a latch | |

both read and write operations can be performed simultaneously |

**Dynamic random-access memory (DRAM)**is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

Soure : https://en.wikipedia.org/wiki/Dynamic_random-access_memory

Question 22 |

Fill in the Blank Type Question |

Initial state is

So,

**the input sea is 10101101001101**

**Hence the number of times ‘Out’ will be 1 is 4.**

Question 23 |

Binary to Gray code converter | |

Binary to XS3 converter | |

Gray to Binary converter | |

None of the above |

Similarly to the encoder one input is high among all and its equivalent binary combination is available at output.

In this case to identify the functionality, let give some arbitrary binary input and observe the output.

Let [X

_{2}X

_{1}X

_{0}] is [1 0 1] respectively then OP

_{5}= IP

_{7}Then [Y

_{2}Y

_{1}Y

_{0}] is [1 1 1]

If [X

_{2}X

_{1}X

_{0}] is [1 1 1] then [OP

_{7}= IP

_{5}] so [Y

_{2}Y

_{1}Y

_{0}= 101] [X

_{2}X

_{1}X

_{0}] is [1 0 0] then [OP

_{4}= IP

_{6}= 1] so [Y

_{2}Y

_{1}Y

_{0}= 110]

From the above we can say that

If input 101 then output is 111

111 101

So input binary and output gray.

Question 24 |

2-to-1 multiplexer | |

4-to-1 multiplexer | |

7-to-1 multiplexer | |

6-to-1 multiplexer |

Question 25 |

for POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction has to be reversed. | |

Memory write operations are slower than memory read operations in an 8085 based system. | |

The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer. | |

Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order. |

POP operation 3 cycles involved: 4T+3T+3T = 107

So in the opcode fetch cycle 2T states are extra in case of push compared to POP and this is needed to decrement the SP.

Question 26 |

B and F | |

A and F | |

H and F | |

A and C |

The shift registers A and F store the result of an addition and the overflow bit.

Question 27 |

Fill in the Blank Type Question |

Question 28 |

Fill in the Blank Type Question |

Question 29 |

Question 30 |

Fill in the Blank Type Question |

Question 31 |

3-input NAND gate | |

3-input XOR gate | |

3-input NOR gate | |

3-input XNOR gate |

Question 32 |

_{1}, D

_{2}, D

_{3}, D

_{4}and D

_{5}, are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle. The average power dissipated (in mW) in the resistor R is_____

Fill in the Blank Type Question |

Question 33 |

_{in}is the input carry and C

_{out}is the output carry. A and B are to be used as the select bits with A being the more significant select bit. Which one of the following statements correctly describes the choice of signals to be connected to the inputs I

_{0}, I

_{1}, c and I

_{3}so that the output is C

_{out}?

I _{0}=0, I_{1}=C_{in}, I_{2}= C_{in} and I_{3} =1 | |

I _{0}=1, I_{1}= C_{in}, I_{2} = C_{in} and I_{3} =1 | |

I _{0} =0, I_{1}=0, I_{2} =1 and I_{3} = C_{in} | |

I _{0}=0, I_{1} = C_{in}, I_{2} =1 and I_{3} = C_{in}, |

**Truth Table for the above circuit**

Question 34 |

The address lines are designated as A15 to A0, where A 15is the most significant address

bit. Which one of the following logic expressions will generate the correct signal for this ROM?

i.e.

0001 0000 0000 0000 H

.

.

.

0010 1111 1111 1111 H

Thus

Question 35 |

^{N}— 1 comparator. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source V

_{in}(whose output is being converted to digital format) has a source resistance of 75 ohms as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full-scale input change for proper conversion. Assume that the time taken by the thermometer to the binary encoder is negligible. If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate?

1 mega samples per second | |

6 mega samples per second | |

64 mega samples per second | |

256 mega samples per second |

Question 36 |

Transitions from State A are ambiguously defined. | |

Transitions from State B are ambiguously defined. | |

Transitions from State C are ambiguously defined. | |

All of the state transitions are defined unambiguously. |

Question 37 |

4E and 0 | |

4E and 1 | |

4F and 0 | |

4F and 1 |

Question 38 |

OR | |

XOR | |

NAND | |

AND |

We can redraw the circuit as

Question 39 |

4 | |

5 | |

6 | |

7 |

Question 40 |

Question 41 |

Fill in the Blank Type Question |

**Case (i) When T = 0**

T

_{total}= NOR Gate Delay + 1st MUX Delay + 2nd MUX Delay

= 2+1.5+1.5 = 5ns

**T**

Case (ii) When T = 1

Case (ii) When T = 1

_{total}= 1st NOT-Gate Delay + 1st MUX Delay + 2nd NOR-Gate Delay + 2nd MUX Delay

= 1+1.5+2+1.5 = 6 ns

**So, the maximum delay = 6 ns.**

Question 42 |

mod-5 counter | |

mod-6 counter | |

Mod-7 counter | |

mod-8 counter |

Question 43 |

a modulo-5 binary up counter | |

a modulo-6 binary down counter | |

a modulo-5 binary down counter | |

a modulo-6 binary up counter |

so it is MOD–5 counter (UP)

From the figure, it can be seen it is basic modulo UP counter configuration because clock is negative edge triggering.

At Modulo-5

1 0 1

For this state, all the 3 flip flops will be set to initial condition.

the states will be= 000,001,010,011,100 at 101 it will reset to 000

Question 44 |

_{1}, D

_{2}and D

_{3}are ideal, an the inputs E

_{1}, E

_{2}and E

_{3}are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?

3-input OR gate | |

3-input NOR gate | |

3-input AND gate | |

3-input XOR gate |

Correct option is (C).

If any of the inputs from

*E*is logic 0 (means 0V) then the corresponding diode will be ‘‘ON’’ resulting in 0V at the output and only when all the inputs are logic 1 (means

_{1}, E_{2}, E_{3}*V*) then

_{DD}*V*(output voltage) will be high, hence, resulting into 3 input AND-gate. Truth table for the logic circuit is shown below.

_{0}Question 45 |

LOOP ADD C (adding the contents of C to accumulator and store it to accumulator)

DCR B (Decrementing the content of registers B)

JNZ LOOP

HLT

Hence, decreasing the number in B as many-time as adding the another number C will result in product of two numbers till value in registers B is zero.

The codes given in option(C), executes the above instructions

Question 46 |

_{2}Y

_{1}Y

_{0}is set to 111. The value of output Y after three clock cycles is

000 | |

001 | |

010 | |

100 |

Question 47 |

Which one of the following statements is TRUE?

Gate 1 is a universal gate | |

Gate 2 is a universal gate | |

Gate 3 is a universal gate | |

None of the gates shown is a universal gate |

If we put Y=0 then Gate-3 is behaving like an Inverter and once inverter can be designed by this gate then It is easy to design AND & OR gate by this.

Gate (1) and Gate (2) don’t have inverter.

Hence Gate (3) is a universal gate.

Question 48 |

NOR gates to NAND gates | |

Inverters to buffers | |

NOR gates no NAND gates and inverters to buffers | |

5 V to ground |

This truth table can be obtained from the given circuit, if we change 5 V to ground.

The desired operation can be achieved by changing

**5V to GND**

Question 49 |

NOR, OR | |

OR, NAND | |

NAND, OR | |

AND, NAND |

Question 50 |

MOV B, M | |

PCHL | |

RNZ | |

SBI BEH |

SBI BEH: Add the content of accumulator with immediate data BE H and store the result in accumulator.

Hence, the correct option is (D).

Question 51 |

mod-2 counter | |

mod-4 counter | |

mod-5 counter | |

mod-6 counter |

Question 52 |

F(X, Y, Z) = Σ(1, 2, 5, 6, 7)

Which one of the product of sums given below is equal to the function F(X, Y, Z)?

Question 53 |

X | |

Y | |

XY | |

X + Y |

Question 54 |

_{3}is __________

52.5 | |

54.5 | |

62.5 | |

64.5 |

So, the frequency at

Question 55 |

Question 56 |

A | |

B | |

C | |

D |

- Essential prime implicants are those which contains atleast one element which is not in any other
- Number of prime implicants in which any of “1” is one time paired, is called Essential Prime Implicants

__Essential prime implicants__

Question 57 |

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

Input A is connected to | |

Input A is connected to | |

Input A is connected to and S is complemented | |

Input A is connected to |

Question 58 |

^{(n-1)}

Question 59 |

1 | |

2 | |

3 | |

4 |

Question 60 |

Question 61 |

W1 | |

W2 | |

W3 | |

W4 |

__Explanation-2__This circuit has used negative edge triggered, so output of the D-flip flop will changed only when CLK signal is going from HIGH to LOW (1 to 0)

This is a synchronous circuit, so both the flip flops will trigger at the same time and will respond on falling edge of the Clock. So, the correct output (Y) waveform is associated to w

_{3}waveform.

Question 62 |

01110… | |

01010… | |

00110… | |

01100… |

So, the output sequence generated at Q1 is 01100….

Question 63 |

_{0}– DI

_{7}) from an external device is shown in the figure. The instruction for correct data transfer is

MVI A, F8H | |

IN F8H | |

OUT F8H | |

LDA F8F8H |

Again to enable the decoder o/p of AND gate must be 1 and signal required is 1 which is the o/p of multi-i/p AND gate to enable I/O device.

So,

Device address = F8F8H

The correct instruction used LDA F8F8H

Question 64 |

Toggle Flip Flop | |

JK Flip Flop | |

SR Latch | |

Master-Slave D Flip Flop |

- Master-Slave D Flip Flop because clock input to both Flip Flops are complement of each other
- Another point is Given circuit diagram is a master slave D flip flop in which master flip-flop works on positive cycle of clock and slave flip-flop works on negative cycle of clock.
- Latches are used to construct Flip-Flop. Latches are level triggered, so if you use two latches in cascaded with inverted clock, then one latch will behave as master and another latch which is having inverted clock will be used as a slave and combined it will behave as a flip-flop. So given circuit is implementing Master-Slave D flip-flop

Question 65 |

Which one of the following Boolean functions is realized by the circuit?

Question 66 |

Question 67 |

Question 68 |

This circuit is CMOS implementation

If the NMOS is connected in series, then the output expression is product of each input with

complement to the final product.

Question 69 |

Question 70 |

170 | |

175 | |

185 | |

195 |

Time after which output carry bit becomes available from the last full adder

= Total number of full adders X Carry propagation delay of full adder

= 16 x 12 ns

= 192 ns

Time after which output sum bit becomes available from the last full adder

= Time taken for its carry in to become available + Sum propagation delay of full adder

= { Total number of full adders before last full adder X Carry propagation delay of full adder } + Sum propagation delay of full adder

= { 15 x 12 ns } + 15 ns

= 195 ns

Question 71 |

_{15}- A

_{8}is

1FH, 1FH, 20H, 12H | |

1FH, FEH, 1FH, FFH, 12H | |

1FH, 1FH, 12H, 12H | |

1FH, 1FH, 12H, 20H, 12H |

Question 72 |

an AND gate | |

an OR gate | |

an XOR gate | |

a NAND gate |

(i.e) lamp glows when switch A & B positions are different.

This truth table simply resembles the logic of a XOR gate as shown below

Form the truth table we can say that XOR logic is implemented

Question 73 |

MVI A, 05 H;

MVI B, 05H;

PTR: ADD B;

DCR B;

JNZ PTR;

ADI 03H;

HLT;

At the end of program, accumulator contains

17 H | |

20H | |

23H | |

05H |

Question 74 |

_{1}has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If is X and Y are digital signals with 0 V as logic 0 and as logic 1, the Boolean expansion for Z is

XY | |

Question 75 |

0C00H–0FFFH. 1C00H-1FFFH. 2C00H-2FFFH, 3C00H-3FFFH | |

1800H-1FFFH. 2800H-2FFFH. 3800H-3FFFH. 4800H-4FFFH | |

0500H-08FFH, 1500H-18FFH. 3500H-38FFH. 5500H-58FFH | |

0800H-0BFFH. 1800H-1BFFH. 2800H-2BFFH. 3800H-3BFFH |

Question 76 |

In this circuit, the race around

Does not occur | |

Occurs when CLK = 0 | |

Occurs when CLK = 1 and A = B = 1 | |

Occurs when CLK = 1 and A = B = 0 |

Question 77 |

4 | |

6 | |

8 | |

10 |

• If B = 00 then there will be three combinations for which OIP will be 1 i.e. when A = 01, 10, or 11.

• If B = 01 there will be two conditions i.e. A = 10 and 11.

• If B = 10 there will be one condition i.e. A = 11.

So total 6 combinations are there for which O/P will be 1.

Question 78 |

So,

Question 79 |

So prime implicants are and .

Question 80 |

Question 81 |

Two bit adder with sum and carry respectively | |

Two bit subtractor with sum and borrow respectively | |

None of the above |

Look at the diagram carefully. Here clearly, carry (C) can be written as:

B

And sum (S) can be written as:

S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A⊕B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)

Refer the Topic Wise Question for Application of Logic Gates Digital Circuits

Question 82 |

_{0}, Q

_{1}and Q

_{2}as output (Q

_{0}Q

_{1}Q

_{2}) after 14 cycles

110 | |

000 | |

001 | |

011 |

Given: A register formed by D flip flops. Here, we have to find the values of the output terminals after 14 cycles.

For determining this, we have to recall all the counter types. See this one is actually johnson counter(Inverted output of the last flip flop is connected to the input of the first flip flop). So, this is a 3 input johnson counter, which means there will be 6 unique states of this counter.

1st Reset is applied and all outputs=000

Next Q

_{0}=1 , Q

_{1}=0 and Q

_{2}=0

Next Q

_{0}=1 , Q

_{1}=1 and Q

_{2}=0

So, like this it will be continued, and on 13th cycle, output states will be:

Q

_{0}=1 , Q

_{1}=0 and Q

_{2}=0

And 14th Cycle: Q

_{0}=1 , Q

_{1}=1 and Q

_{2}=0

Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits

Question 83 |

26.0 V | |

16.3 V | |

10.3 V | |

8.1 V |

_{2}= (26)

_{10}

V

_{DAC}= resolution x (decimal equivalents)

∴V

_{DAC}= 8.1 V

Question 84 |

5.1 V and 0.3% | |

4.6 V and 0.4% | |

5.1 V and 0.4% | |

4.6 V and 0.3% |

__Full scale output__Resolution = step size = 20 mV

V

_{FS}= (2

^{8}–1) × resolution

= 255 × 20 mV

∴

**V**

_{FS}= 5.1V

__Resolution__% resolution =

∴

**% resolution = 0.4%**

Question 85 |

The simplification of this by using theorems of Boolean algebra will be

A + B | |

A ⨁ B | |

(A + B) (A . B) | |

A . B |

Question 86 |

AA + BB + CC | |

ABC + BCA + CAB | |

AB + AC | |

AB + AC + BC |

∴ F = BC + AC + AB + ABC

∴ ∴ F = AB + BC + AC

Question 87 |

Arithmetic instruction | |

Data transfer instructions | |

Logical instructions | |

Machine control instructions |

**Data Transfer Instructions**These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group −

### Instruction to transfer a word

**MOV**− Used to copy the byte or word from the provided source to the provided destination.**PPUSH**− Used to put a word at the top of the stack.**POP**− Used to get a word from the top of the stack to the provided location.**PUSHA**− Used to put all the registers into the stack.**POPA**− Used to get words from the stack to all registers.**XCHG**− Used to exchange the data from two locations.**XLAT**− Used to translate a byte in AL using a table in the memory.

### Instructions for input and output port transfer

**IN**− Used to read a byte or word from the provided port to the accumulator.**OUT**− Used to send out a byte or word from the accumulator to the provided port.

### Instructions to transfer the address

**LEA**− Used to load the address of operand into the provided register.**LDS**− Used to load DS register and other provided register from the memory**LES**− Used to load ES register and other provided register from the memory.

### Instructions to transfer flag registers

**LAHF**− Used to load AH with the low byte of the flag register.**SAHF**− Used to store AH register to low byte of the flag register.**PUSHF**− Used to copy the flag register at the top of the stack.**POPF**− Used to copy a word at the top of the stack to the flag register.

Question 88 |

synchronous counter | |

ripple counter | |

ring counter | |

up counter |

Question 89 |

32 | |

16 | |

8 | |

4 |

**An ‘n’ bit shift register needs ‘n’ number of flip flops.**

So, the 8 bit shift register needs ‘8’ number of flip flops.

So, the 8 bit shift register needs ‘8’ number of flip flops.

Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.

The registers which will shift the bits to left are called “Shift left registers”.

The registers which will shift the bits to right are called “Shift right registers”.

Shift registers are basically of 4 types. These are:

Serial In Serial Out shift register

Serial In parallel Out shift register

Parallel In Serial Out shift register

Parallel In parallel Out shift register

**Note :**Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to store n bits of data. A Register is a device which is used to store such information. It is a group of flip flops connected in series used to store multiple bits of data. The information stored within these registers can be transferred with the help of shift registers

Question 90 |

00010111 | |

00010001 | |

01110111 | |

10001001 |

_{10}1000

(9)

_{10}1001

← 6 is added due to carry generated

∴(8)

_{10}+ (9)

_{10}= (17)

_{10}

∴(17)

_{10}= [0001 0111]

_{BCD}

**Theory**BCD or Binary Coded Decimal is that number system or code which represents the 10 decimal digits in terms of binary numbers.

The following is table for Decimal number and it’s Binary Equivalent:

As seen above, when the Decimal equivalent exceeds 9, then we start writing the BCD equivalent as two Binary equivalents.

Now let’s have a look at some examples:

0101 + 0011 = 1000 (Binary addition). [If you compare this with the above table, you’ll find that 0101 is 5; 0011 is 3 and 1000 is 8.] We can do the same for every number whose sum comes to less than or equal to 9.

But if the addition is greater than 9,then what!

Simple! Let’s take an example:

0101 + 1000 = 1101 . [From table, 0101 is 5; 1000 is 8 and 1101 is 13.]

But the BCD equivalent of 13 is 0001 0011.

So we take the Binary addition obtained i.e 1101 and add 0110 (decimal 6) to it.

The result obtained is 1101 + 0110 = 1 0011 where the last 4 bits 0011 represent 3 and 1(can also be written as 0001, which means 1 in decimal equivalent). Thus we obtain 0001 0011 as final answer!

Thus, for any addition greater than 9, add binary equivalent of 6 to the Binary sum obtained and you’ll get it’s BCD equivalent.

Hope it helps. 🙂

Credits : Shukriya!

Question 91 |

001000101 | |

10100100 | |

11100110 | |

10100101 |

**Gray to Binary Code Converter**From the above operation, finally we can get the binary values like

b3 = g3,

b2 = b3 XOR g2,

b1= b2 XOR g1,

b0 = b1 XOR g0.

Question 92 |

-42 | |

-86 | |

-116 | |

-170 |

Question 93 |

1) the output is a function of the current state and inputs

2) the output is a function of only the current state

Which of the following machines are respectively correct for these styles?

Mealy machine and Moore machine | |

Moore machine and Mealy machine | |

State machine and Mealy machine | |

State machine and State machine |

Mealy Machine |
Moore Machine |
---|---|

Output depends both upon the present state and the present input | Output depends only upon the present state. |

Generally, it has fewer states than Moore Machine. | Generally, it has more states than Mealy Machine. |

The value of the output function is a function of the transitions and the changes, when the input logic on the present state is done. | The value of the output function is a function of the current state and the changes at the clock edges, whenever state changes occur. |

Mealy machines react faster to inputs. They generally react in the same clock cycle. | In Moore machines, more logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later. |

Question 94 |

DMA controller | |

read-write controller | |

high-speed controller | |

master-slave controller |

**Direct Memory Access:**

The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU.

**This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit**

Question 95 |

OUT <8-bit port address> | |

IN <8-bit port address> | |

OUT R<8-bit port address> | |

IN R < 8-bit port address> |

Question 96 |

El

MVl A, 08H

SlM

It means

disable all interrupts | |

enable all interrupts | |

disable RST 7.5 and 6.5 | |

enable RST 7.5 and 6.5 |

MVI A, 08H → load accumulator with 08H

SIM → set interrupt mask

∴ Data of A is copied to 5IM

A has (0000 1000)

_{2}

Question 97 |

jump 15 bytes relative to the program counter | |

copy and load 15 words in reverse direction to the program counter | |

move to a location by 15 bits to the program counter | |

redirect (jump) to a location by 15 words relative to the program counter |

It should be JC OX 15 which means jump by 15 bytes if carry is zero relative to program counter.

Question 98 |

1) Selecting the microcontroller as a controlling device

2) Selecting the language to write the software

3) Partitioning the tasks between hardware and software to optimize the cost

Select the correct answer using the code given below

1, 2 and 3 | |

1 and 2 only | |

1 and 3 only | |

2 and 3 only |

- Microcontroller is selected as controlling device
- Language is selected to write the program (software) without difficulties.
- Partioning the tasks between hardware and software to optimize the case.

Question 99 |

**Statement (I):**Sign-magnitude representation is rarely used in implementing the integer of the ALU.

**Statement (II):**There are two representations of zero in sign-magnitude representation.

Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I) | |

Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I) | |

Statement (I) is true but Statement (II) is false | |

Statement (I) is false but Statement (II) is true |

**1)**In sign magnitude form and 1’s complement form, the disadvantage is ‘0’ has two representations.

**2)**Only 2’s complement form has unique representation of 0. Hence 2’s complement form is preferred.

In sign-magnitude format, MSB decides the sign. If MSB is 0 then sign is positive and if MSB is 1, then sign is negative (i.e. number is negative)

e.g. For 3 bit sign magnitude representation

**000 -> +0**

**100 -> -0**

Hence statement (II) is correct explanation of statement (I).

**1. Signed Magnitude Method :**

In the signed magnitude method number is divided into two parts: Sign bit and magnitude. Sign bit is 1 for negative number and 0 for positive number. Magnitude of number is represented with the binary form of the number.

**2. 2’s Complement Method :**

In 2’s complement method, positive numbers are represented in the same way as they are represented in sign magnitude method. But if the number is negative, first represent the number with positive sign and then take 2’s complement of that number.

**Difference between Signed Magnitude and 2’s Complement Method :**

SIGNED MAGNITUDE METHOD |
2’S COMPLEMENT METHOD |
---|---|

It is a method to denote fixed point signed numbers. | It is also used to denote fixed point signed numbers. |

Number is divided into two parts. | Number is considered as a whole. |

Sign bit is considered explicitly. | Sign bit is not considered explicitly. |

Additional hardware is required for resultant sign of arithmetic. | No additional hardware is required in 2’s complement method. |

Addition and subtraction are performed on separate hardware. | Addition and subtraction are performed by using adder only. |

It has two different representation for 0. One is +0 and second is -0. (+0 : 0000 0000) & (-0 : 1000 0000) | 0 has only one representation for -0 and +0 (+0 or -0 : 0000 0000). |

It is non-weighted system. | It assigns negative weight to the sign bit. |

Question 100 |

B =

6.02(2 ^{7}-30) dB | |

6.02(2 ^{8}-31) dB | |

6.02(2 ^{7}-31) dB | |

6.02(2 ^{8}-30) dB |

Dynamic range =

Therefore , for 32-bit binary number (B),

dynamic range = →31(6.02)dB

for floating point number (F) ,

dynamic range= → (6.02)dB

now , required difference is = 31(6.02)dB - (6.02)dB

= 6.03()

Refer the Topic Wise Question for Number Systems Digital Circuits

Question 101 |

If Sys clock frequncy is > 4 * clk_ext frequency. What is the functionality of above circuit?

Falling Edge detector with Pulse width of Q _{out} = one cycle of Sys clk | |

Rising Edge detector with Pulse width of Q _{out} = one cycle of Sys clk | |

Falling Edge detector with Pulse width of Q _{out} = one cycle of clk_ext | |

Rising Edge detector with Pulse width of Q _{out} = one cycle of clk_ext |

D flip-flop is level triggered.

Sys clock frequncy is > 4 * clk_ext frequency.

It will detect the rising edge of clock external input , but with a delay of seconds and width of pulse =.

Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits

Question 102 |

w+x+y+z | |

y’ + w’z’+xz’ | |

y +w’z’+xz | |

x+z’w’y+x’ |

k-map for given boolean exoression:

F(w,x,y,z)= +

=

Refer the Topic Wise Question for Minimization Digital Circuits

Question 103 |

0.4V, 0.4V | |

0.4V, 1V | |

1V, 0.4V | |

1V, 1V |

in a digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.

Refer the Topic Wise Question for Logic Families Digital Circuits

Question 104 |

entity test is

port

(

data : in std_logic;

clk : in std_logic;

rset : in std_logic;

q : out std_logic

);

end test;

architcture behav of test is

begin

process (clk)

begin

if (clk’event and clk =’1’) then

if (reset =’0’) then

q <= ‘0’;

else

q <= data;

end if;

end if;

end process;

end behav;

VERILOG

module test (data, clk, reset, q);

input data, clk, reset;

output q;

reg q;

always @ (posedge clk)

if (reset)

q = 1’b0;

else q = data;

endmodule

The Above Verilog/VHDL module depicts which sequential element:

Rising edge Flip-flop with synchrounus Reset | |

Falling edge Flip-flop with synchrounus Reset | |

Rising edge Flip-flop with asynchrounus Reset | |

Falling edge Flip-flop with asynchrounus Reset |

in the given programming , ‘if’ condition is used to check occurrence of rising edge . and as RESET is used with every clock cycle that indicates it is synchronous.

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 105 |

MOV A, #27h

MOV R1, A

SWAP A

ANLA, # OFH

MOV B, #10

MULAB

MOV R2, A

MOV A, #R1

ANL A, #0FH

ADD A, R2

00011011 | |

01110010 | |

01010101 | |

11001011 |

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 106 |

0x800C | |

0x803C | |

0x801F | |

0x840 |

microcontroller follows byte addressing storage method, even though it is 16-bit controller ,each address location stores only 1 bye.

Given 2’Dimensional array A[5][7] has total of 5 rows and 7 column. Array will be stored in memory by each row wise. Each row is having 7 elements , each of 2 bytes (16bits), which requires total of 14bytes(72).

Address of A[4][2]= ++

= +(

=

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 107 |

Unsigned char flag = 0x7C;

flag=flag | 0x80;

flag=flag | (1<<4);

flag&=~(1<<7);

flag^=(1<<6);

0x1C | |

0x20 | |

0x24 | |

0x3C |

Unsigned char flag = 0x7C;

flag=01111100

flag=flag | 0x80;

it is bitwise OR operation.

Flag =00111100=0x3C

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 108 |

6 ms, 12ms | |

6 ms, 10 ms | |

4 ms, 4 ms | |

4 ms, 6 ms |

Round robin is a CPU scheduling algorithm where each process is assigned a fixed time slot in a cyclic way.

Turnaround time (TAT) is the time interval from the time of submission of a process to the time of the completion of the process. It can also be considered as the sum of the time periods spent waiting to get into memory or ready queue, execution on CPU and executing input/output

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 109 |

B) Synthesis

C) Static Timing Analysis

D) Place and Route

E) Programming file generation

What is the correct order of FPGA design flow?

A,B,C,D,E | |

A,B,D,C,E | |

B,D,C,E,A | |

C,A,D,E,B |

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 110 |

Response | |

Throughput | |

Security | |

Portability |

**Operational Quality Attributes.**:- These are attributes related to operation or functioning of an embedded system. The way an embedded system operates affects its overall quality. Some of the Operational Attributes are:

•Response

•Throughput

•Reliability

•Maintainability

•Security

•Safety

**Non Operational Attributes :-**These are attributes

**not**related to operation or functioning of an embedded system. The way an embedded system operates affects its overall quality.These are the attributes that are associated with the embedded system before it can be put in operation. Some of non-operational attributes are :

•Testability and Debug-ability

•Evolvability

•Portability

•Time to prototype and market

•Per unit and total cost

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 111 |

Time elapse : MOV R0, #100

Part 1 : MOV R1, #50

Part 2 : MOV R2, #248

Part 3 : DJNZ R2, Part3

: DJNZ R1, Part2

: DJNZ R0, Part1

Assumptions:

•Microcontroller is running at 12 MHz frequency and 1 machine cycle is having 12 clock cycles

•MOV instruction takes 1 Machine cycle

•DJNZ instruction takes 2 Machine cycle

Calculate time required for execution of Part 1

2495600 | |

2496300 | |

2495300 | |

2496600 |

calculation of execution time for part-3:

1 machine cycle=12 = 12 =1

Code in part will be executed 248 times, so part3 execution time is

=248

DJNZ instruction takes 2 Machine cycle

=248

= 496

Code in part 2 will executed 50 times. So execution time for part 2 is

=50[1]

=50(499)

Code in part 1 will executed 100 times. So execution time for part 1 is

=100[1 +50(499)+2]

=2495300

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 112 |

B) Generate LCALL to ISR

C) Complete Execution of instruction in progress

D) Clear the interrupt flag

E) Set interrupt in progress

Correct order of execution of action taken by 8051 micro-controllers when an interrupt occurs:

C,A,D,E,B | |

A,B,D,E,C | |

C,D,B,E,A, | |

A,C,B,D,E |

when an interrupt occurs:

(i) Microcontroller finishes the instruction it is executing.

(ii) Then it saves the address of next instructions (PC) on the stack.

(iii) It jumps to a fixed location in memory called the interrupt vector table that holds the address of the interrupt service routine.

(iv) Then it generates LCALL to ISR. After executing ISR, the microcontroller returns to the place where it was interrupted.

Refer the Topic Wise Question for Microprocessor Digital Circuits

Question 113 |

_{0}, I

_{1}, I

_{2}and I

_{3}as input

A=

B.

The above circuit is

4:1 Multiplexer | |

De-Multiplexer | |

BCD circuit | |

Priority Encoder |

It is a priority encoder. A priority encoder(4 bit) is basically used to convert 4-bit input to equivalent binary representation. It takes in 4-bit as input, and has 2 bits at the output end. The truth table for a 4 x 2 priority encoder is generally given as:

Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits

Question 114 |

The output Z

AB | |

ABC | |

ABC + AB | |

ABC +B |

First let us systematically approach for this, and determine Y

_{1}

So, Y

_{1}= C+ Next Y

_{2}=ABC, and finally Y

_{3}= A(

So, on reduction, Y

_{3}can be written as: Y

_{3}=ABC

Now, Z= Y

_{3}+Y

_{2}=> ABC +ABC=> ABC

Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits

Question 115 |

The frequency of signal x is fs and the shift register is clocked at the positive edge of 2fs. The time offset between A and B is

1/(2fs) | |

1/fs | |

3/(2fs) | |

1/(4fs) |

Here a shift register is given. We have to determine the time offset between A and B.

So, here it is given that the frequency of the signal if 2f

_{s}. 2f

_{s}frequency means time will be T

_{s}/2(T

_{s}being time).

So, now, So, T

_{s}/2 is the first time. That is the time at which it has reached point A. We have to find time offset, which means that the time difference between A and B(when data reaches each point).

So, Ts/2 => Point A. Next 3Ts/2=> Point B. Similarly it will continue if other points are there. Now, Time offset= difference in time

So, difference in time between the two= 3Ts/2 -(Ts/2)=Ts. But in options only fs is given. Now we know that Ts=1/fs. So, answer will be option (b)

Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits

Question 116 |

_{1}, V

_{2}and V

_{3}with 1:2:1 power ratings respectively. The power supply is designed with the distribute power conversion scheme as shown in the following figure. What is the overall power conversion efficiency?

We have to determine overall power conversion efficiency. Now, efficiency(ո) is generally given as: V

_{out}/V

_{in}

From the diagram it is clear that V

_{out}= V1+2V2+V3(1+2+1=4V)

Now, we have to find out V

_{in}. Since ո= V

_{out}/V

_{in}, so V

_{in}= Vout/ո

Vout=4 V, and Vout=V1+2V2+V3=> V1(X)+V2(Y)+V3(Z)

So, V

_{in}= X+(Y/ո2)+(Z/ո3)/ ո1

Replacing X by V, we get:

Vin=V(ո2ո3+2ո3+ո2)/ո2ո3ո1........ (a)

So, now substituting Vout=4 and Vin from (a), we will get option (a).

Refer the Topic Wise Question for Data Converters Digital Circuits

Question 117 |

Static RAM stores data in the form of charge | |

They have low capacity, but offer high speed | |

It doesn't require periodic refreshing | |

They are made up of six transistor |

Static Random Access memory(SRAM) uses six transistors to store a single bit. SRAM retains data bits as long as there is power. SRAM doesn't have to be periodically refreshed. Only wrong option is option (a)

Refer the Topic Wise Question for Semiconductor Memories Digital Circuits

Question 118 |

De-Multiplexer | |

Multiplexer | |

Y= I _{0} (A_{0}+ A_{1}) | |

Y = I _{0} (+ A_{0}) |

For answering this, we first have to find out the output expression, and then based on that expression, we can determine what circuit actually it is.

So, from the figure, we can write:

Y=A

_{0}I

_{0}+A

_{1}=> See this expression. It means that A

_{0}will be on the output line whenever I

_{0}=1, and A

_{1}will be on the output line whenever I

_{0}=0. So, totally two inputs and one select line. Clearly this is a 2 x 1 multiplexer circuit.

Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits