Digital Circuits | Subject Wise

The Correct Answer Among All the Options is D

By rearranging the circuit,

Truth table:

The functionality of the above circuit is XNOR

From the diagram
carry (C) can be written as: B

sum (S) can be written as:
S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A⊕B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)

From the diagram
carry (C) can be written as: B

sum (S) can be written as:
S= A + = A

So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A⊕B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)

This is a very interesting question and we can get answer quickly if we use smart way to solve it. The circuit is called a Switchtail counter or Johnson counter . An N-bit Johnson counter has 2N states and it recycles after 2N clocks. The given counter has 3 bits, so it recycles after 6 clocks. The initial state is not given, so let us assume it to be 000. After 12 clocks it will return to 000. After thirteenth clock it will be 100. After fourteenth clock it will be 110.
Hence Option(A) is the correct answer.

According to the given data,
Green is turned ON for 70 seconds
Yellow is turned ON for 5 seconds
Red is turned ON for 75 seconds
Total time to complete one cycle for all 3 lights = (70 + 5 +75) seconds = 150 seconds
Time period of available clock = 5 seconds
Total number of unique states required

Minimum number of flip-flops required is,

flip flops are required for the stable output to make transition error zero and false triggering of output.

Number of distinct values of X3 X2 X1 X0 (out of the 16 possible values)
that give Y = 1 is 8.

The following can be observed,
When otherwise
When otherwise
So, and

Hence,

Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

Soure : https://en.wikipedia.org/wiki/Dynamic_random-access_memory

Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

Soure : https://en.wikipedia.org/wiki/Dynamic_random-access_memory

From the state diagram, let us obtain the transition of states and out when IN channel.
Initial state is
So, the input sea is 10101101001101 Hence the number of times ‘Out’ will be 1 is 4.

As we know in a decoder w.r.t any binary input combination the corresponding output pin is high and remaining low.
Similarly to the encoder one input is high among all and its equivalent binary combination is available at output.
In this case to identify the functionality, let give some arbitrary binary input and observe the output.
Let [X₂ X₁ X₀] is [1 0 1] respectively then OP₅  = IP₇ Then [Y₂ Y₁ Y₀] is [1 1 1]
If [X₂ X₁ X₀] is [1 1 1] then [OP₇ = IP₅ ] so [Y₂ Y₁ Y₀= 101] [X₂ X₁ X₀] is [1 0 0] then [OP₄ = IP₆ = 1] so [Y₂ Y₁ Y₀= 110]
From the above we can say that
If input 101 then output is 111
111 101 
So input binary and output gray.

In push operation 3 cycles involved: 6T+3T+3T = 127
POP operation 3 cycles involved: 4T+3T+3T = 107
So in the opcode fetch cycle 2T states are extra in case of push compared to POP and this is needed to decrement the SP.

In an 8085 microprocessor, after performing the addition, result is stored in accumulator and if any carry (overflow bit) is generated it updates flags.
The shift registers A and F store the result of an addition and the overflow bit.

The Correct Answer Among All the Options is B

Truth Table for the above circuit

Address varying from 1000 H to 2FFFH
i.e.
0001 0000 0000 0000 H
.
.
.
0010 1111 1111 1111 H

Thus

All the transistor are NMOS. We know when input to gate is 0, NMOS behave as open circuit. If input to Gate is 1, NMOS is short circuit.
We can redraw the circuit as

Case (i) When T = 0
T_total = NOR Gate Delay + 1st MUX Delay + 2nd MUX Delay
= 2+1.5+1.5 = 5ns
Case (ii) When T = 1
T_total = 1st NOT-Gate Delay + 1st MUX Delay + 2nd NOR-Gate Delay + 2nd MUX Delay
= 1+1.5+2+1.5 = 6 ns
So, the maximum delay = 6 ns.

Since 1 0 1 -> state becomes 0 0 0
so it is MOD–5 counter (UP)

From the figure, it can be seen it is basic modulo UP counter configuration because clock is negative edge triggering.
At Modulo-5
1 0 1
For this state, all the 3 flip flops will be set to initial condition.
the states will be= 000,001,010,011,100 at 101 it will reset to 000 

The Correct Answer Among All the Options is C
Correct option is (C).
If any of the inputs from E₁, E₂, E₃ is logic 0 (means 0V) then the corresponding diode will be ‘‘ON’’ resulting in 0V at the output and only when all the inputs are logic 1 (means V_DD) then V₀ (output voltage) will be high, hence, resulting into 3 input AND-gate. Truth table for the logic circuit is shown below.

MVI A 00H (loading the accumulator with OOH)
LOOP ADD C (adding the contents of C to accumulator and store it to accumulator)
DCR B (Decrementing the content of registers B)
JNZ LOOP
HLT
Hence, decreasing the number in B as many-time as adding the another number C will result in product of two numbers till value in registers B is zero.
The codes given in option(C), executes the above instructions

For a universal gate, it consist of one basic gate (AND, OR) and inverter (NOT gate).
If we put Y=0 then Gate-3 is behaving like an Inverter and once inverter can be designed by this gate then It is easy to design AND & OR gate by this.
Gate (1) and Gate (2) don’t have inverter.
Hence Gate (3) is a universal gate.

SR latch truth table is given below.

This truth table can be obtained from the given circuit, if we change 5 V to ground.
The desired operation can be achieved by changing 5V to GND

Generally arithmetic or logical instructions update the data of accumulator and flags. So, in the given option only SBI BEH is arithmetic instruction.
SBI BEH: Add the content of accumulator with immediate data BE H and store the result in accumulator.
Hence, the correct option is (D).

We observed that the Given circuit is a Ripple counter or Asynchrnous counter. In Ripple counter, o/p frequency of each flip-flop is half of the input frequency if their all the states are used otherwise o/p frequency of the counter is
So, the frequency at

Essential prime implicants
• Essential prime implicants are those which contains atleast one element which is not in any other
• Number of prime implicants in which any of “1” is one time paired, is called Essential Prime Implicants

For an n-variable Boolean function, the maximum number of prime implicants = 2^(n-1)

In packed BCD (Binary Coded Decimal) typically encoded two decimal digits within a single byte by taking advantage of the fact that four bits are enough to represent the range 0 to 9. So, 1856357 is required 4-bytes to stored these BCD digits

Explanation-2
This circuit has used negative edge triggered, so output of the D-flip flop will changed only when CLK signal is going from HIGH to LOW (1 to 0)

This is a synchronous circuit, so both the flip flops will trigger at the same time and will respond on falling edge of the Clock. So, the correct output (Y) waveform is associated to w₃ waveform.

So, the output sequence generated at Q1 is 01100….

This circuit diagram indicating that it is memory mapped I/O because to enable the 3-to-8 decoderis required active low signal through is required active low through it means I/o device read the status of device LDA instruction is appropriate with device address.
Again to enable the decoder o/p of AND gate must be 1 and signal required is 1 which is the o/p of multi-i/p AND gate to enable I/O device.
So,

Device address = F8F8H
The correct instruction used LDA F8F8H

1. Master-Slave D Flip Flop because clock input to both Flip Flops are complement of each other
2. Another point is Given circuit diagram is a master slave D flip flop in which master flip-flop works on positive cycle of clock and slave flip-flop works on negative cycle of clock.
3. Latches are used to construct Flip-Flop. Latches are level triggered, so if you use two latches in cascaded with inverted clock, then one latch will behave as master and another latch which is having inverted clock will be used as a slave and combined it will behave as a flip-flop. So given circuit is implementing Master-Slave D flip-flop

This circuit is CMOS implementation
If the NMOS is connected in series, then the output expression is product of each input with
complement to the final product.

Consider the last full adder for worst case delay.
Time after which output carry bit becomes available from the last full adder
= Total number of full adders X Carry propagation delay of full adder
= 16 x 12 ns
= 192 ns

Time after which output sum bit becomes available from the last full adder
= Time taken for its carry in to become available + Sum propagation delay of full adder
= { Total number of full adders before last full adder X Carry propagation delay of full adder } + Sum propagation delay of full adder
= { 15 x 12 ns } + 15 ns
= 195 ns

The purpose of staircase wiring is, one should be able to switch on and switch off lights from more than one point and these can be achieved by 2-way switches.The position of switches A, B and the condition of the lamp can be tabulated as below.

(i.e)  lamp glows when  switch A & B positions are different.
This truth table simply resembles the logic of a XOR gate as shown below

Form the truth table we can say that XOR logic is implemented

Output will be 1 if A > B.

• If B = 00 then there will be three combinations for which OIP will be 1 i.e. when A = 01, 10, or 11.
• If B = 01 there will be two conditions i.e. A = 10 and 11.
• If B = 10 there will be one condition i.e. A = 11.
So total 6 combinations are there for which O/P will be 1.

Series combination of n-mos is equivalent to AND and parallel combination is equivalent to OR.
So,

The Karnaugh Map of the given function is shown below


So prime implicants are and .

The Correct Answer Among All the Options is B
Look at the diagram carefully. Here clearly, carry (C) can be written as:
B
And sum (S) can be written as:
S= A + = A
So, option (C) and (D) are wrong. So, remaining is (a) and (b). For half adder, we have S= A⊕B and C=AB. No option matches. So, next is option (b), which is a two bit subtractor. So, obviously answer is option (b)
Refer the Topic Wise Question for Application of Logic Gates Digital Circuits

The Correct Answer Among All the Options is A
Given: A register formed by D flip flops. Here, we have to find the values of the output terminals after 14 cycles.
For determining this, we have to recall all the counter types. See this one is actually johnson counter(Inverted output of the last flip flop is connected to the input of the first flip flop). So, this is a 3 input johnson counter, which means there will be 6 unique states of this counter.
1st Reset is applied and all outputs=000
Next Q₀=1 , Q₁=0 and Q₂=0
Next Q₀=1 , Q₁=1 and Q₂=0
So, like this it will be continued, and on 13th cycle, output states will be:
Q₀=1 , Q₁=0 and Q₂=0
And 14th Cycle: Q₀=1 , Q₁=1 and Q₂=0
Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits

(11010)₂ = (26)₁₀
V_DAC = resolution x (decimal equivalents)

∴V_DAC = 8.1 V

Full scale output
Resolution = step size = 20 mV
V_FS = (2⁸–1) × resolution
= 255 × 20 mV
∴ V_FS = 5.1V

Resolution
% resolution =

∴ % resolution = 0.4%

∴ F = BC + AC + AB + ABC
∴ ∴ F = AB + BC + AC

Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group −

Instruction to transfer a word

• MOV − Used to copy the byte or word from the provided source to the provided destination.
• PPUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

• IN − Used to read a byte or word from the provided port to the accumulator.
• OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
• PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag register.

An ‘n’ bit shift register needs ‘n’ number of flip flops.
So, the 8 bit shift register needs ‘8’ number of flip flops.

Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can be made to move within the registers and in/out of the registers by applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.

Shift registers are basically of 4 types. These are:
Serial In Serial Out shift register
Serial In parallel Out shift register
Parallel In Serial Out shift register
Parallel In parallel Out shift register

Note : Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to store n bits of data. A Register is a device which is used to store such information. It is a group of flip flops connected in series used to store multiple bits of data. The information stored within these registers can be transferred with the help of shift registers

(8)₁₀1000
(9)₁₀ 1001
← 6 is added due to carry generated
∴(8)₁₀ + (9)₁₀ = (17)₁₀
∴(17)₁₀ = [0001 0111]_BCD

Theory

Gray code = 10100101

Gray to Binary Code Converter

From the above operation, finally we can get the binary values like
b3 = g3,
b2 = b3 XOR g2,
b1= b2 XOR g1,
b0 = b1 XOR g0.

Mealy Machine	Moore Machine
Output depends both upon the present state and the present input	Output depends only upon the present state.
Generally, it has fewer states than Moore Machine.	Generally, it has more states than Mealy Machine.
The value of the output function is a function of the transitions and the changes, when the input logic on the present state is done.	The value of the output function is a function of the current state and the changes at the clock edges, whenever state changes occur.
Mealy machines react faster to inputs. They generally react in the same clock cycle.	In Moore machines, more logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later.

Direct Memory Access:
The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit

IN (8-bit port address) 1 byte is for opcode and 1 byte for 8 bit port address so it is a 2 Byte instruction and this instruction is used to accept the data from the inport port and load this data into accumulator.

EI → means enable all maskable interrupts
MVI A, 08H → load accumulator with 08H
SIM → set interrupt mask
∴ Data of A is copied to 5IM
A has (0000 1000)₂

Micro processor does not have any instruction such as BC so it is a printing mistake
It should be JC OX 15 which means jump by 15 bytes if carry is zero relative to program counter.

Following constraints are to be considered by the designer while designing an embedded system :

• Microcontroller is selected as controlling device
• Language is selected to write the program (software) without difficulties.
• Partioning the tasks between hardware and software to optimize the case.

In modern computer system 2’s complement representation is used.
1) In sign magnitude form and 1’s complement form, the disadvantage is ‘0’ has two representations.
2) Only 2’s complement form has unique representation of 0. Hence 2’s complement form is preferred.

In sign-magnitude format, MSB decides the sign. If MSB is 0 then sign is positive and if MSB is 1, then sign is negative (i.e. number is negative)
e.g. For 3 bit sign magnitude representation
000 -> +0
100 -> -0
Hence statement (II) is correct explanation of statement (I).

1. Signed Magnitude Method :
In the signed magnitude method number is divided into two parts: Sign bit and magnitude. Sign bit is 1 for negative number and 0 for positive number. Magnitude of number is represented with the binary form of the number.

2. 2’s Complement Method :
In 2’s complement method, positive numbers are represented in the same way as they are represented in sign magnitude method. But if the number is negative, first represent the number with positive sign and then take 2’s complement of that number.

Difference between Signed Magnitude and 2’s Complement Method :

SIGNED MAGNITUDE METHOD	2’S COMPLEMENT METHOD
It is a method to denote fixed point signed numbers.	It is also used to denote fixed point signed numbers.
Number is divided into two parts.	Number is considered as a whole.
Sign bit is considered explicitly.	Sign bit is not considered explicitly.
Additional hardware is required for resultant sign of arithmetic.	No additional hardware is required in 2’s complement method.
Addition and subtraction are performed on separate hardware.	Addition and subtraction are performed by using adder only.
It has two different representation for 0. One is +0 and second is -0. (+0 : 0000 0000) & (-0 : 1000 0000)	0 has only one representation for -0 and +0 (+0 or -0 : 0000 0000).
It is non-weighted system.	It assigns negative weight to the sign bit.

The Correct Answer Among All the Options is B
Dynamic range =
Therefore , for 32-bit binary number (B),
dynamic range = →31(6.02)dB
for floating point number (F) ,
dynamic range= → (6.02)dB
now , required difference is = 31(6.02)dB - (6.02)dB
= 6.03()
Refer the Topic Wise Question for Number Systems Digital Circuits

The Correct Answer Among All the Options is B
D flip-flop is level triggered.
Sys clock frequncy is > 4 * clk_ext frequency.
It will detect the rising edge of clock external input , but with a delay of seconds and width of pulse =.
Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits

The Correct Answer Among All the Options is B
k-map for given boolean exoression:

F(w,x,y,z)= +
=
Refer the Topic Wise Question for Minimization Digital Circuits

The Correct Answer Among All the Options is B
in a digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.
Refer the Topic Wise Question for Logic Families Digital Circuits

The Correct Answer Among All the Options is A
in the given programming , ‘if’ condition is used to check occurrence of rising edge . and as RESET is used with every clock cycle that indicates it is synchronous.
Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is A

Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is B
microcontroller follows byte addressing storage method, even though it is 16-bit controller ,each address location stores only 1 bye.
Given 2’Dimensional array A[5][7] has total of 5 rows and 7 column. Array will be stored in memory by each row wise. Each row is having 7 elements , each of 2 bytes (16bits), which requires total of 14bytes(72).
Address of A[4][2]= ++
= +(
=

Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is D
Unsigned char flag = 0x7C;
flag=01111100
flag=flag | 0x80;
it is bitwise OR operation.

Flag =00111100=0x3C
Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is A
Round robin is a CPU scheduling algorithm where each process is assigned a fixed time slot in a cyclic way.
Turnaround time (TAT) is the time interval from the time of submission of a process to the time of the completion of the process. It can also be considered as the sum of the time periods spent waiting to get into memory or ready queue, execution on CPU and executing input/output
Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is B

Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is D
Operational Quality Attributes.:- These are attributes related to operation or functioning of an embedded system. The way an embedded system operates affects its overall quality. Some of the Operational Attributes are:
•Response
•Throughput
•Reliability
•Maintainability
•Security
•Safety
Non Operational Attributes :- These are attributes not related to operation or functioning of an embedded system. The way an embedded system operates affects its overall quality.These are the attributes that are associated with the embedded system before it can be put in operation. Some of non-operational attributes are :
•Testability and Debug-ability
•Evolvability
•Portability
•Time to prototype and market
•Per unit and total cost
Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is C
calculation of execution time for part-3:

1 machine cycle=12 = 12 =1

Code in part will be executed 248 times, so part3 execution time is
=248
DJNZ instruction takes 2 Machine cycle
=248
= 496
Code in part 2 will executed 50 times. So execution time for part 2 is
=50[1]
=50(499)
Code in part 1 will executed 100 times. So execution time for part 1 is
=100[1 +50(499)+2]
=2495300
Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is A
when an interrupt occurs:
(i) Microcontroller finishes the instruction it is executing.
(ii) Then it saves the address of next instructions (PC) on the stack.
(iii) It jumps to a fixed location in memory called the interrupt vector table that holds the address of the interrupt service routine.
(iv) Then it generates LCALL to ISR. After executing ISR, the microcontroller returns to the place where it was interrupted.
Refer the Topic Wise Question for Microprocessor Digital Circuits

The Correct Answer Among All the Options is D
It is a priority encoder. A priority encoder(4 bit) is basically used to convert 4-bit input to equivalent binary representation. It takes in 4-bit as input, and has 2 bits at the output end. The truth table for a 4 x 2 priority encoder is generally given as:

Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits

The Correct Answer Among All the Options is B
First let us systematically approach for this, and determine Y₁
So, Y₁= C+ Next Y₂=ABC, and finally Y₃= A(
So, on reduction, Y₃ can be written as: Y₃=ABC
Now, Z= Y₃+Y₂=> ABC +ABC=> ABC
Refer the Topic Wise Question for Circuits and Code Converters Digital Circuits

The Correct Answer Among All the Options is B
Here a shift register is given. We have to determine the time offset between A and B.
So, here it is given that the frequency of the signal if 2f_s. 2f_s frequency means time will be T_s/2(T_s being time).
So, now, So, T_s/2 is the first time. That is the time at which it has reached point A. We have to find time offset, which means that the time difference between A and B(when data reaches each point).
So, Ts/2 => Point A. Next 3Ts/2=> Point B. Similarly it will continue if other points are there. Now, Time offset= difference in time
So, difference in time between the two= 3Ts/2 -(Ts/2)=Ts. But in options only fs is given. Now we know that Ts=1/fs. So, answer will be option (b)
Refer the Topic Wise Question for Flip Flops and Counters Digital Circuits

The Correct Answer Among All the Options is A
We have to determine overall power conversion efficiency. Now, efficiency(ո) is generally given as: V_out/V_in
From the diagram it is clear that V_out= V1+2V2+V3(1+2+1=4V)
Now, we have to find out V_in. Since ո= V_out/V_in, so V_in= Vout/ո
Vout=4 V, and Vout=V1+2V2+V3=> V1(X)+V2(Y)+V3(Z)
So, V_in= X+(Y/ո2)+(Z/ո3)/ ո1
Replacing X by V, we get:
Vin=V(ո2ո3+2ո3+ո2)/ո2ո3ո1........ (a)
So, now substituting Vout=4 and Vin from (a), we will get option (a).
Refer the Topic Wise Question for Data Converters Digital Circuits

The Correct Answer Among All the Options is A
Static Random Access memory(SRAM) uses six transistors to store a single bit. SRAM retains data bits as long as there is power. SRAM doesn't have to be periodically refreshed. Only wrong option is option (a)
Refer the Topic Wise Question for Semiconductor Memories Digital Circuits