Computer Organization | Subject Wise

Microprogramming is a process of writing microcode for a microprocessor. Microcode is low-level code that defines how a microprocessor should function when it executes machine-language instructions. Typically, one machine language instruction translates into several microcode instruction, on some computers, the microcode is stored in ROM and can not be modified;

Reference : https://www.ques10.com/p/11119/what-is-microprogramming-draw-and-explain-micro--1/

Given Bit String: D4FE2003
converting in to Binary D4FE2003 = 1101 0100 1111 1110 0010 0000 0000 0011
Total bits = 32
Number of vacant tracks i.e. with value 0 = 18
Number of occupied tracks i.e. with value 1 =14
Thus Percentage occupied tracks = 14/32 * 100 = 43.75% ≃ 44%
so, Nearest percentage is 44%

• Memory-mapped I/O uses the same address space to address both memory and I/O devices.
• The memory and registers of the I/O devices are mapped to (associated with) address values.
• So when an address is accessed by the CPU, it may refer to a portion of physical RAM, or it can instead refer to
• memory of the I/O device. Thus, the CPU instructions used to access the memory can also be used for accessing devices.
• Each I/O device monitors the CPU's address bus and responds to any CPU access of an address assigned to that device, connecting the data bus to the desired device's hardware register.
• To accommodate the I/O devices, areas of the addresses used by the CPU must be reserved for I/O and must not be available for normal physical memory.
• The reservation may be permanent, or temporary (as achieved via bank switching). An example of the latter is found in the Commodore 64, which uses a form of memory mapping to cause RAM or I/O hardware to appear in the 0xD000-0xDFFF range.

Reference : https://en.wikipedia.org/wiki/Memory-mapped_I/O

Give Memory capacity = 2^m Kbytes  =2^m + 2¹⁰ bytes =2^m+10 bytes (k can written as 2¹⁰)
Therefore m+10 bits are required to represented the Whole memory
Similarly 2ⁿ operations can be represented by using n bits.
Now instruction form

So Instruction operator1,operator 2,operator 3. Will take 3m+30+n bits

Reference : https://books.google.co.in/books?

When a user enter's a bit. CPU process the bit and it is written back by any of the output peripheral like screen or the printer.
Here, the peripheral refers to the output devices. The output devices may be a monitor, or pen drive or a disc.
Every peripheral device is controlled by writing and reading its registers

The Principle of Locality of Reference justifies the use of cache Memory.
In other words, Locality of Reference refers to the tendency of the computer program to access instructions whose addresses are near one another.

locality of reference. There are two ways with which data or instruction is fetched from main memory and get stored in cache memory. These two ways are the following:

Temporal Locality :
Temporal locality means current data or instruction that is being fetched may be needed soon.
In Temporal Locality The Least Recently Algorithm is Used (LRU)
Clustering in time: items referenced in the immediate past have a high probability of being re-referenced in the immediate future

Spatial Locality:
Spatial locality means instruction or data near to the current memory location that is being fetched, may be needed soon in the near future.
Clustering in space: items located physically near an item referenced in the immediate past have a high probability of being re-referenced in the immediate future  

Refer : https://www.cs.usask.ca/faculty/bunt/presentations/Locality.ppt 

The baud rate is the rate at which information is transferred in a communication channel. Serial ports use two-level (binary) signaling, so the data rate in bits per second is equal to the symbol rate in bauds.
 Reference: https://en.wikipedia.org/wiki/Serial_port#Speed.
"2400 baud" means that the serial port is capable of transferring a maximum of 2400 bits per second."
So, transmission rate here = 2400 bps

For asynchronous communication we require start and stop bits,
Total bit per character = 8 bit data + 2 stop bit +1 start bit = 11 bits
no of characters = 2400/11 = 218.18
for transmitted characters we take floor i.e,. 218

For synchronous communication, we don't need start and stop bits.
Number of 8 bit characters that can be transmitted per second = 2400/8 = 300

Big-endian and little-endian are terms that describe the order in which a sequence of bytes are stored in computer memory.
- A big-endian system stores the most significant byte of a word at the smallest memory address and the least significant byte at the largest.
- A little-endian system, in contrast, stores the least-significant byte at the smallest address.
Reference : https://en.wikipedia.org/wiki/Endianness#:~:text=A%20big%2Dendian%20system%20stores,sized%20groups%20of%20binary%20bits.

X: Indirect Addressing - Pointers
Y: Immediate Addressing - Constants
Z: Auto Decrement Addressing - Loop

Indirect  addressing mode the instruction does not have the address of the data to be operated on, but the instruction points where the address is stored(it is indirectly specifying the address of memory location where the data is stored or to be stored)

 immediate addressing mode the data is to be used is immediately given in instruction itself;so it deals with constant data.

Autodecrement addressing mode,  Before determining the effective address, the value in the base register is decremented by the size of the data item which is to be accessed.

Within a loop, this addressing mode can be used to step backwards through all the elements of an array or vector.

There are five interrupt  signals TRAP,RST 7.5,RST 6.5,RST 5.5 and INTR.

Maskable Interrupts are those which can be disabled or ignored by the microprocessor. These interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.

Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as edge triggering and is used in critical power failure conditions.

Given
Hit ratio of cache = 0.8
Cache Access Time = 30 ns
Memory Access Time = 150 ns
CPU Access Time = Cache Hit * Cache Access Time + (1 – Cache Hit)(Cache Access Time+ Memory Access Time)
CPU Access Time= 0.8 * 30 + 0.2 * (30 + 150) = 60 ns

Note : Effective Memory Access Time and Average Access Time both are same

Raid level 5 is very similar to raid 0. The data is striped across all disks. Remember raid level 0 is not redundant. If you lose a disk, you lose your data. With raid level 5, things are a little different.

This level uses a concept called, distributed parity, to protect against a disk failure. If you lose any disk in a raid level 5 configuration, the surviving disks can continue to operate because of the parity. In raid 5 the the parity is distributed across all disks in the raid group.
Reference : https://www.what-is-my-computer.com/raid-5.html

Given Sequence:
4, 34, 10, 7, 19, 73, 2, 15, 6, 20


Since shortest seek time first policy is used, head will first move to 34. This move will cause 16*1 ms. After 34, head will move to 20 which will cause 14*1 ms. And so on....
Head starts from cylinder 50, the order followed is : 34, 20, 19, 15, 10, 7, 6, 4, 2, 73
Total head movements incurred while servicing these requests
= (50 – 34) + (34 – 20) + (20 – 19) + (19 – 15) + (15 – 10) + (10 – 7) + (7 – 6) + (6 – 4) + (4 – 2) + (73 – 2)
= 16 + 14 + 1 + 4 + 5 + 3 + 1 + 2 + 2 + 71
= 119
Time taken for one head movement = 1 msec. So,
Time taken for 119 head movements = 119 x 1 msec = 119 msec

8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage
All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1 MB physical address space (2^20 = 1,048,576).

Therefore 16 bit data lines and 20 address lines.
20 lines means 2²⁰ byte = 1 mega byte

Pipelining is a method to execute a program breaking it in several independent sequence of stages

• Option(A) True
  Total delay will be Max (All delays) + Register Delay.
• Option(B) True
  If data forwarding is not there then
  Example:
  SUB R9,R4,R5
  ADD R6,R9,R4 //Register R9 result will be dependent on first instruction.
• Option(C) True
  ID and EX shares ID/EX register.

Temporal locality refers to the reuse of specific data and/or resources within relatively small time durations.
Spatial locality refers to the use of data elements within relatively close storage locations.
To exploit the spatial locality, more than one word are put into cache block.
References: http://en.wikipedia.org/wiki/Locality_of_reference

The Principle of Locality of Reference justifies the use of cache Memory.
In other words, Locality of Reference refers to the tendency of the computer program to access instructions whose addresses are near one another.

locality of reference. There are two ways with which data or instruction is fetched from main memory and get stored in cache memory. These two ways are the following:

Temporal Locality :
Temporal locality means current data or instruction that is being fetched may be needed soon.
In Temporal Locality The Least Recently Algorithm is Used (LRU)
Clustering in time: items referenced in the immediate past have a high probability of being re-referenced in the immediate future

Spatial Locality:
Spatial locality means instruction or data near to the current memory location that is being fetched, may be needed soon in the near future.
Increasing the block size of the cache comes under this
Clustering in space: items located physically near an item referenced in the immediate past have a high probability of being re-referenced in the immediate future  

Refer : https://www.cs.usask.ca/faculty/bunt/presentations/Locality.ppt 

A vectored interrupt is an I/O interrupt that tells the computer that handles I/O interrupts at the hardware level that a request for attention from an I/O device has been received and and also identifies the device that sent the request.
I/O interruption that informs the portion of the machine that manages device-level I/O interrupts that such a demand for action has already been provided from a device as well as defines the machine that sent the application.
Reference : https://en.wikipedia.org/wiki/Vectored_Interrupt

Assume Accumulator is 8 bit
MVI : Move Immediate data to a register or memory location.
ACI : Add immediate to accumulator with carry.
XRA : The content of accumulator are exclusive OR with specified register or memory location

In 1^st instruction execution then the value of Accumulator is
A = 30H = 0011 0000
In 2^nd instruction execution then the value of Accumulator is
A = 30+30 = 60H = 0110 0000
In 3^rd instruction execution then the value of Accumulator is
A = A⊕A = 0110 0000 ⊕ 0110 0000 = 0000 0000 = 00H

Execution of the last instruction has no effect on the contents of Accumulator. Thereby, the answer remains the same because
In 8085 microprocessor, POP H is interpreted as:
Content at the memory location pointed stack pointer is copied into register pair specified in instruction operand field i.e, HL pair in this case.

Single Instruction, Multiple Data (SIMD) units refer to hardware components that perform the same operation on multiple data operands concurrently. Typically, a SIMD unit receives as input two vectors (each one with a set of operands), performs the same operation on both sets of operands (one operand from each vector), and outputs a vector with the results.

Reference : https://www.sciencedirect.com/topics/computer-science/single-instruction-multiple-data

See Why : https://www.quora.com/What-computers-do-not-use-a-von-Neumann-architecture

What is SIMD : https://www.quora.com/What-is-SIMD

--A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.
Reference : https://en.wikipedia.org/wiki/Control_register

--Interface is a device which is used to connect a peripheral devices to bus.


--A communication protocol is a system of rules that allow two or more entities of a communications system to transmit information via any kind of variation of a physical quantity. The protocol defines the rules, syntax, semantics and synchronization of communication and possible error recovery methods. Protocols may be implemented by hardware, software, or a combination of both.
Reference : https://en.wikipedia.org/wiki/Communication_protocol#:~:text=A%20communication%20protocol%20is%20a,and%20possible%20error%20recovery%20methods.

There are five interrupt  signals TRAP,RST 7.5,RST 6.5,RST 5.5 and INTR.

Maskable Interrupts are those which can be disabled or ignored by the microprocessor. These interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.

Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as edge triggering and is used in critical power failure conditions.

Memory Address Register (MAR) holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. MAR, which is found inside the CPU, goes either to the RAM (random access memory) or cache. The memory address register is half of a minimal interface between a microprogram and computer storage; the other half is a memory data register. In general, MAR is a parallel load register that contains the next memory address to be manipulated. For example, the next address to be read or written.

Reference : https://en.wikipedia.org/wiki/Memory_address_register

• Self reallocating code required for Displacement Addressing Mode. Auto Increment is useful for Array implementation
• In Auto increment/decrement Addressing Mode , Register will be automatically incremented or decremented So, ALU is required. But additional ALU is not required.
• For incrementing the data, the auto-increment addressing mode is used which purely depends on the size of the data.  In Auto increment mode automatically increments the contents of a register by a value that corresponds to the size of the accessed operand. Thus , the increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit operands. The size of the operand is usually specified as part of the operation code of an instruction.

In Index mode addressing mode, the effective address of the operand is generated by adding a constant value to the contents of a register. The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code. Index Mode is used to access an array whose elements are in successive memory locations. The content of the instruction code, represents the starting address of the array and the value of the index register, and the index value of the current element. By incrementing or decrementing index register different element of the array can be accessed. The term addressing modes refers to the way in which the operand of an instruction is specified. Information contained in the instruction code is the value of the operand or the address of the result/operand.

Case 1 : If I3 is executed assuming without other interrupts(Min Time required ):
Time interval = Interrupt Response time + Execution time
Time interval= 4.5 + 20 = 24.5 microseconds

Case 2 : If I3 is executed simultaneously with other interrupts(Max Time required):
All instructions are present.
Time interval = Interrupt Response time + Execution time for I1, I2, I3
Time interval=I1+I2+I3 ={(4.5+25) +(4.5+35) +(4.5+20) } =93.5
So possible range of I3 24.5 microsecond to 93.5 microsecond .

It is a technique for compensating the relatively slow speed of DRAM(Dynamic RAM). In this technique, the main memory is divided into memory banks which can be accessed individually without any dependency on the other.

In interleaved memory, memory addresses are allocated to separate memory banks. In an interleaved system with two memory banks (assuming word-addressable memory), if some logical address belongs to bank 0, then the consecutive logical address would belong to bank 1, next logical would again belong to bank 0, and so on.

An interleaved memory is said to be n-way interleaved when there are n banks and memory location i resides in bank i mod n.

2-Way Interleaved
Two memory blocks are accessed at same time for writing and reading operations. So, organizing the memory into two banks would be termed as Two-way memory interleaving.

It means that we have 8 inputs to the MUX so it is 8:1 MUX and therefore it require 3 select inputs.
Which makes Y = 3.
Number  of bits in control memory =26
Number  of bits in control memory next address field=26-13-3 =10
10 bit addressing .we have 2¹⁰=1024 memory size
So X,Y size=10,3

Each address is multiple of 3 as the starting address is 300 and is each instruction consists of 24 bit, i.e., 3 byte.

Size of instruction = 24/8 = 3 bytes.

Program Counter can shift 3 bytes at a time to jump to next instruction.

Thus, in the given options the valid counter will be the one which is the multiple of 3.only 600 is satisfied.

Given
N.o of surfaces = 16
N.o of tracks per surface = 128
N.o of sectors per track = 256
N.o of bytes per sector = 512 bytes

Capacity of disk pack = (Total number of surfaces * Number of tracks per surface * Number of sectors per track * Number of bytes per sector)
= 16 * 128 * 256 * 512 bytes
= 2²⁸ bytes
= 2⁸ * 2²⁰ bytes
= 256 MB

  Total number of sectors = (Total number of surfaces * Number of tracks per surface * Number of sectors per track)
= 16 * 128 * 256 sectors
= 2¹⁹ sectors
So, We require 19 bits to address the sector

• Relative addressing cannot be faster than absolute addressing as absolute address must be calculated from relative address.
• Absolute addresses are directly available in the Instruction address field itself so there is no need to calculate the Effective Address of operand
• Relative addressing mode we need to calculate the Effective Address by adding some relative value to the PC so it requires some calculation so it is slower than absolute addressing

• CPU continuously checks the status bit of interrupt at the completion of each current instruction running when there is a interrupt it service the interrupt using Interrupt Service Routine (ISR)
• An interrupt service routine (ISR) is a software routine that hardware invokes in response to an interrupt. ISR examines an interrupt and determines how to handle it executes the handling, and then returns a logical interrupt value. If no further handling is required the ISR notifies the kernel with a return value. An ISR must perform very quickly to avoid slowing down the operation of the device and the operation of all lower-priority ISRs.

CISC	RISC
Focus on software	Focus on hardware
Uses only Hardwired control unit	Uses both hardwired and micro programmed control unit
Transistors are used for more registers	Transistors are used for storing complex Instructions
Fixed sized instructions	Variable sized instructions
Can perform only Register to Register Arthmetic operations	Can perform REG to REG or REG to MEM or MEM to MEM
Requires more number of registers	Requires less number of registers
Code size is large	Code size is small
A instruction execute in single clock cycle	Instruction take more than one clock cycle
A instruction fit in one word	Instruction are larger than size of one word
A large number of instructions are present in the architecture.	Very fewer instructions are present. The number of instructions are generally less than 100.
Some instructions with long execution times. These include instructions that copy an entire block from one part of memory to another and others that copy multiple registers to and from memory.	No instruction with a long execution time due to very simple instruction set. Some early RISC machines did not even have an integer multiply instruction, requiring compilers to implement multiplication as a sequence of additions.
Variable-length encodings of the instructions. Example: IA32 instruction size can range from 1 to 15 bytes.	Fixed-length encodings of the instructions are used. Example: In IA32, generally all instructions are encoded as 4 bytes.
Multiple formats are supported for specifying operands. A memory operand specifier can have many different combinations of displacement, base and index registers.	Simple addressing formats are supported. Only base and displacement addressing is allowed.
CISC supports array.	RISC does not supports array.
Arithmetic and logical operations can be applied to both memory and register operands.	Arithmetic and logical operations only use register operands. Memory referencing is only allowed by load and store instructions, i.e. reading from memory into a register and writing from a register to memory respectively.
Implementation programs are hidden from machine level programs. The ISA provides a clean abstraction between programs and how they get executed.	Implementation programs exposed to machine level programs. Few RISC machines do not allow specific instruction sequences.
Condition codes are used.	No condition codes are used.
The stack is being used for procedure arguments and return addresses.	Registers are being used for procedure arguments and return addresses. Memory references can be avoided by some procedures.

In synchronous I/O process performing I/O operation will be placed in blocked state till the I/O operation is completed. An ISR will be invoked after the completion of I/O operation and it will place process from block state to ready state.

In asynchronous I/O, a process need not stay in the blocked state until the I/O is complete. It can place a request for I/O to the kernel, and resume with the execution. After the I/O operation is completed, a signal is directed to the process notifying the completion.

Order of instruction cycle phases
IF ID EX WB
There will be operand forwarding between first and second instructions and 2nd and 3rd instructions

Total No. of cycles required =8

Cycle Time in Non-Pipelined Processor 
Frequency of the clock = 2.5 gigahertz
Cycle time = 1 / frequency
Cycle time= 1 / (2.5 gigahertz)
Cycle time= 1 / (2.5 x 10⁹ hertz)
Cycle time= 0.4 ns

Non-pipeline execution time to process 1 instruction = Number of clock cycles taken to execute one instruction
1 Instruction Execution Time = 4 clock cycles
1 Instruction Execution Time = 4 x 0.4 ns
1 Instruction Execution Time = 1.6 ns

  Cycle Time in Pipelined Processor :  
Frequency of the clock = 2 gigahertz
Cycle time Cycle time= 1 / frequency
Cycle time= 1 / (2 gigahertz)
Cycle time= 1 / (2 x 10⁹ hertz)
Cycle time= 0.5 ns

  Pipeline Execution Time : Since there are no stalls in the pipeline, so ideally one instruction is executed per clock cycle. So,
Pipeline execution time
= 1 clock cycle
= 0.5 ns
Speed up  = ( Non-pipeline execution time / Pipeline execution time )
= 1.6 ns / 0.5 ns
= 3.2

Given
N.o of surfaces = 16
N.o of tracks per surface = 128
N.o of sectors per track = 256
N.o of bytes per sector = 512 bytes

Capacity of disk pack = (Total number of surfaces * Number of tracks per surface * Number of sectors per track * Number of bytes per sector)
= 16 * 128 * 256 * 512 bytes
= 2²⁸ bytes
= 2⁸ * 2²⁰ bytes
= 256 MB

  Total number of sectors = (Total number of surfaces * Number of tracks per surface * Number of sectors per track)
= 16 * 128 * 256 sectors
= 2¹⁹ sectors
So, We require 19 bits to address the sector

Register renaming is done to avoid WAR (Write after Read) and WAW (Write after Write) data hazards.
Refer this link for more information : https://en.wikipedia.org/wiki/Register_renaming

SISD (single instruction stream, single data stream) is a computer architecture in which a single uni-core processor executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture.

SISD is one of the four main classifications as defined in Flynn's taxonomy.

Reference : https://en.wikipedia.org/wiki/SISD#:~:text=This%20corresponds%20to%20the%20von,present%20in%20the%20computer%20architecture.

Relative Addressing Mode

• Relative mode addressing is most relevant to writing a position-independent code i.e. Program Relocation at run time
• To change the normal sequence of execution of instructions
• For branch type instructions since it directly updates the program counter

Average access time = [ H₁*T₁]+[(1-H₁)*H₂*T₂]+[ (1-H₁)(1-H₂)*H_m*T_m ]

where,

H₁ = Hit rate of level 1 cache = 0.8
T₁ = Access time for level 1 cache = 1 ns
H₂ = Hit rate of level 2 cache = 0.9
T₂ = Access time for level 2 cache = 10 ns
H_m = Hit rate of Main Memory = 1
T_m = Access time for Main Memory = 500 ns

Average Access Time   = ( 0.8 * 1 ) + ( 0.2 * 0.9 * 10 ) + ( 0.2 * 0.1 * 1 * 500) = 0.8 + 1.8 + 10

So, Average Access Time= 12.6 ns

We have to transfer contents of AL to memory location whose address is in BX

Let Register BX content is 202020 // Memory Location

Register AL content is 20

Effective Address EA =[BX] = 202020 // Content of Register BX

so AL contents 20 is moved to memory location 202020

This is an example of Register Indirect Addressing Mode

Basic DMA operation

• The direct memory access (DMA) I/O technique provides direct access to the memory while the microprocessor is temporarily disabled.
• A DMA controller temporarily borrows the address bus, data bus, and control bus from the microprocessor and transfers the data bytes directly between an I/O port and a series of memory locations.
•  The DMA transfer is also used to do high-speed memory-to memory transfers.
• Two control signals are used to request and acknowledge  a DMA transfer in the microprocessor-based system.
• The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses after the current bus cycle.
•  The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released control of its buses by placing the buses at their high-impedance states.
•  The HOLD input has a higher priority than the INTR or NMI interrupt inputs.

Refer : http://www.unife.it/ing/lm.infoauto/sistemi-elaborazione/dispense/csf04_12.pdf

First version: 5Mhz processor and 8-bit bus.

Second version: 20Mhz processor and 32-bit bus.

The second version is the best as compared to first version because second version has both high bandwidth as well as increased CPU speed
Increasing the bandwidth aids in achieving the maximum speed up.

max(20/5, 32/8) = 4

Hence we will take the maximum of these speedups which is 4.

• Associative memory is suitable for parallel searches and is used where search time needs to be minimized
• In  K-way associativity we have k comparators which compares the tag bits of 'k' blocks in parallel.

DMA performs data transfer operation. The different DMA transfer modes are as follows:
1) Burst or block transfer DMA
2) Cycle steal or single byte transfer DMA.
3) Transparent or hidden DMA.

1) Burst or block transfer DMA

• It is the fastest DMA mode. In this two or more data bytes are transferred continuously.
• Processor is disconnected from system bus during DMA transfer. N number of machine cycles are adopted into the machine cycles of the processor where N is the number of bytes to be transferred.
• DMA sends HOLD signal to processor to request for system bus and waits for HLDA signal.
• After receiving HLDA signal, DMA gains control of system bus and transfers one byte. After transferring one byte, it increments memory address, decrements counter and transfers next byte.
• In this way, it transfer all data bytes between memory and I/O devices. After transferring all data bytes, the DMA controller disables HOLD signal & enters into slave mode.

2) Cycle steal or single byte transfer DMA.

• In this mode only one byte is transferred at a time. This is slower than burst DMA.
• DMA sends HOLD signal to processor and waits for HLDA signal on receiving HLDA signal, it gains control of system bus and executes only one DMA cycle.
• After transfer one byte, it disables HOLD signal and enters into slave mode.
• Processor gains control of system bus and executes next machine cycle. If count is not zero and data is available then the DMA controller sends HOLD signal to the processor and transfer next byte of data block.

3) Transparent or Hidden DMA transfer

• Processor executes some states during which is floats the address and data buses. During this process, processor is isolated from the system bus.
• DMA transfers data between memory and I/O devices during these states. This operation is transparent to the processor.
• This is slowest DMA transfer. In this mode, the instruction execution speed of processor is not reduced. But, the transparent DMA requires logic to detect the states when the processor is floating the buses

Reference : https://www.ques10.com/p/11180/explain-various-dma-transfer-modes-in-brief-with-1/

Given
Total No of Block = 64
Block size = 16 B

Memory Block Number = Byte Address / Block size
= 1206/16 = 75
Given byte address 1206 is a part of 75th block in Main Memory.

Now we have to find a cache block number where it Map to memory block number.

Cache block number = (Memory block number) mod (number of blocks in cache)
= 75 mod 16
= 11

Speed Up= Time without Pipeline / Time with Pipeline

For non pipeline processor,
It takes, 12 cycles to complete 1 instruction
So, for n instructions it will take 12n cycle

Time required in a pipelined processor = (k + n - 1) tp
where, k = number of stages in pipeline unit.
n = number of instructions
tp = execution time unit(take maximum time in all stages i.e, 6 will the maximum in this case )

So, Speed Up = Time without Pipeline / Time with Pipeline
= 12n / (6 + n - 1)6
= 12n /(n + 5)6
= 12n /6n
= 2

Given
   Segment base (CS) = 0x1000
   Offset (IP) = 0xE000

In 8086 the address bus is 20 bit, The address is generated by using segment base and offset.
it means Address = segment * 0x10 + Offset (Here segment is multiplied by 10h)

Address= segment*0x10+offset
Address=CS*0x10+IP =0x1000*0x10+0xe000
Thus Address =0x1E000

option(b) is the correct answer
Refer: https://books.google.co.in/books?id=t9

JNZ instruction means Jump if ZF = 0  i.e. if accumulator is not empty. AL will contain 0000 0000, on incrementing it will be 0000 0001 and so on. It is a 8-bit register so maximum it can hold value = 2⁸ = 256. After this accumulator will get overflow and it becomes 0. So, Loop will continue for 256 times.

Assumption : "Cache is faster than main memory" is not sufficient to answer this question precisely. It should be given that "Cache is how many times faster than the main memory".

So I am Assume Cache is faster than memory by at least 10 times

However with the given information we can guarantee that speed up has to be strictly less than 5.

We first access Cache memory and Main memory is accessed only on a cache miss

Speed Gain = [ (Memory Access Time without Cache) / (Memory Access Time with Cache) ]
where
Tm = Memory Access Time
Tc  = Cache Access Time

Speed Gain = (Tm) / (Tc + 0.20*Tm)
Speed Gain = [ (1) / ( (Tc/Tm) + 0.20 ) ]

Let (Tc/Tm) = x, 0 < x ≤ 0.1 ( Since cache (say last level cache) is faster than memory by at least 10 times (10 times because otherwise there is not much advantage of using a cache))

Speed Gain = [ (1) / ( (x) + 0.20 ) ]
3.33 ≤ Speed Gain < 5

Given
Speedup factor = 6
Efficiency = 70% (0.7)

Efficiency Formula :
Efficiency = Speedup factor / Number of stages
0.7 = 6 / No. of stages
No. of stages = 8.56 = 9

DMA usually operates in Cycle Stealing Mode, where it transfers 1 byte per cycle. // Default assumption.

Given DMA module transferring characters at = 9600 bps = 9600/8 Bps = 1200 Bytes per sec

Processor is fetching instructions at the rate = 1 MIPS (million instruction per second) = 10⁶

So time will the processor be slowed down due to DMA activity =  = 1200/10⁶ = 12*1000/10⁴ ms  = 1.2 ms

A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.

Total Memory access time is 60 ns + 10ns = 70 ns

CPU frequency is 33 MHz means 1 clock time is 1 / (33*10⁶) = .03030 * 10^-6 sec = 30.30 ns

Number of wait states = No. of clocks to need = 70 ns / 30.30 ns = 2.31  ≈ 3

  So no. of wait states 3.

Reference: https://en.wikipedia.org/wiki/Wait_state

C-SCAN because it has been started from 100th and serving all the right hand side request till the last point then reverse the direction and starts from track 0 to serve further request.


In above diagram starts from 100, 126,167, and after reaching 199, without servicing any request during return it will reach initially, then it start servicing requests on the way from 0 (12,36,42,51,69 and 76)

CMOS may refer to any of the following
Alternatively referred to as a RTC (real-time clock), NVRAM (non-volatile RAM) or CMOS RAM, CMOS is short for complementary metal-oxide semiconductor. CMOS is an onboard, battery powered semiconductor chip inside computers that stores information. This information ranges from the system time and date to system hardware settings for your computer.

• Decoder = N inputs  to  2^N  outputs
• Mux         = Many to One  i.e. 2^N  Inputs  to  1 output
• De-Mux = One to Many i.e. 1 to 2^N output

Step 1: Given  binary number:

000110101101

Step 2: Group all the digits in sets of four starting from the LSB (far right). Add zeros to the left of the last digit if there aren't enough digits to make a set of four:

0001 1010 1101

Step 3: Use below information to convert  into an hexadecimal digit:

0001 = 1, 1010 = A, 1101 = D

So, 1AD is is the hexadecimal equivalent to the decimal number 110101101.

Information
(0-9) no difference from 10 onwards
1010 – A
1011 – B
1100 – C
1101 – D
1110 – E
1111 – F

Asynchronous or ripple counters

2 bit ripple up counter: It contains two flip flops. A 2-bit ripple counter can count up to 4 states. It counts from 0 to 3.


2 bit ripple down counter: It contains two flip flops. A 2-bit ripple counter can count up to 4 states. It is known as down counter as it counts down from 3 to 0.

→  Maskable Interrupt: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor.

→ Exception: unplanned interrupts while executing a program is called Exception. For example: while executing a program if we got a value which should be divided by zero is called a exception

→ Synchronous interrupt will happen every time an instruction executes (with a given program state)
Examples of Synchronous interrupt:
– Divide by zero
– System call
– Bad pointer dereference
Reference : https://www.cs.unc.edu/~porter/courses/comp530/f18
Reference : https://www.electronicshub.org/types-of-interrupts

Cache mapping is performed using following three different techniques :

1. Direct Mapping
2. Fully Associative Mapping
3. K-way Set Associative Mapping

• I/O devices are identified by 16-bit addresses
• 8085 communicates with an I/O device as if it were one of the memory locations
• Memory related instructions are used
      For e.g. LDA, STA

LDA 8000H
Loads A with data read from input device with 16-bit address 8000H
STA 8001H
Stores (Outputs) contents of A to output device with 16-bit address 8001H

Reading a number from input port (port address 8000H) and display it on ASCII display connected to output port (port address 8001H)

• LDA 8000H  ; reads data value 03H (example)into ; Accumulator, A = 03H
• MVI B, 30H  ;  loads register B with 30H
• ADD B            ;   A = 33H, ASCII code for 3
• STA 8001H   ;  display 3 on ASCII display

Option(D) is Most Appropriate

• ALU is the computational center of the CPU. It performs all mathematical and logical operations.
• The accumulator is a register in which intermediate arithmetic and logic results are stored.
• Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation. Access to main memory is slower than access to a register like the accumulator

Reference : https://en.wikipedia.org/wiki/Accumulator_(computing)

2048*4 means that you have:

• 2048 locations
• 4 bits per location

It means that a memory of 2048 words, where each word is 4 bits.
So to address 2048 we need 11 bits (2¹¹=2048),
so 11 address lines.

MIMD stands for 'Multiple Instruction and Multiple Data Stream'.

• Now a days ,All processors in a parallel computer can execute different instructions and operate on various data at the same time.
• In MIMD, each processor has a separate program and an instruction stream is generated from each program
• MIMD is a technique employed to achieve parallelism. Machines using MIMD have a number of processors that function asynchronously and independently. At any time, different processors may be executing different instructions on different pieces of data.

Reference : 
https://en.wikipedia.org/wiki/MIMD#:~:text=In%20computing%2C%20MIMD%20(multiple%20instruction,on%20different%20pieces%20of%20data.

Reference : https://www.javatpoint.com/mimd

 Subroutine 
A set of Instructions which are used repeatedly in a program can be referred to as Subroutine. Only one copy of this Instruction is stored in the memory. When a Subroutine is required it can be called many times during the Execution of a Particular program. A call Subroutine Instruction calls the Subroutine. Care Should be taken while returning a Subroutine as Subroutine can be called from a different place from the memory.

The content of the PC must be Saved by the call Subroutine Instruction to make a correct return to the calling program.

Refer : https://www.quora.com/How-did-the-call-instruction-work-in-the-8085-microprocessor

Refer : https://www.geeksforgeeks.org/subroutine-subroutine-nestin.

• Start and Stop bits are used in asynchronous communication as a means of timing or synchronizing the data characters being transmitted.
• Start bit is used to signal the beginning of a frame.
• Stop bit is used to signal the end of a frame.

microprogramming is a systematic technique for implementing the control logic of a computer's central processing unit. It is a form of stored-program logic that substitutes for hardwired control circuitry.

STC : It is logical instruction or logical instruction used to set the carry flag in a computer.

Data Transfer 
The data transfer instructions move data between registers or between memory and registers.
MOV , MVI,LDA,STA,LHLD,SHLD etc.

Logical 
The Instructions under this group perform logical operation such as AND, OR, compare, rotate etc.
Examples are: ANA, XRA, ORA, CMP,  RAL,STC etc.

Program control
instructions change or modify the flow of a program. The most basic kind of program control is the unconditional branch or unconditional jump. Branch is usually an indication of a short change relative to the current program counter. Jump is usually an indication of a change in program counter that is not directly related to the current program counter (such as a jump to an absolute memory location or a jump using a dynamic or static table), and is often free of distance limits from the current program counter.
LOOPNZ,RET,CALL,LOOPZ,IRET,JUMP,JUMPNZ etc.

• A subroutine can be implemented by using CALL and RET instructions.
• CALL instruction when used decrements the stack pointer by two.
• RET instruction increments the stack pointer register by two.
• A processor with no stack pointer register cannot have a subroutine call instruction.

• A wait state is a situation in which the computer processor experiences a delay, mainly when accessing external memory or a device that is slow in its response.
• program or processor is waiting for the completion of some event before resuming activity. A program or process in a wait state is inactive for the duration of the wait state
• Computer microprocessors generally run much faster than the computer's other subsystems
• When the processor needs to access external memory, it starts placing the address of the requested information on the address bus
• It then must wait for the answer, each of the cycles spent waiting is called a wait state
• Thus, wait states helps to interface slow peripherals to the memory

Access time of hard disk is defined as time to access one word from hard disk memory

It is given that 30 rotations per second.

• 30 rotations = 1 sec
• 1 rotation = 1/30 sec

It is given that Capacity of each track 300 words
It means in 1 rotation, we can access 300 words

• 1 rotation = 300 words
• 1 word = 1/300 rotations

So, 1 word transfer time = (1/300) *(1/30) sec

Rotational delay = Average taken to be the time to rotate by half = 1/2 x time for 1 rotation = 1/2 X 1/30 seconds = 1/60 s = 16.6667 ms

Avg access time= 30 ms(seek time)+ 1/60 sec (Rotational Delay)+ 1/9000 sec (transfer time)
Avg access time= 30 ms + 16.6667 ms + 0.1111 ms
Avg access time= 46.78 ms

 

Indirect	1 bit
Address	Given Address 256kB    28 (256kB) * 210 (1024 bytes/kB) = 218 == 18 bits
Registers	Total 64 registers = 26 = 6 bits
OP-code	32 - 1 - 18 - 6 bits = 7 bits

Average Access time = [H₁*T₁] + [ (1-H₁) * H₂*T₂   ]  +  [  (1-H₁)  (1-H₂) *  H_m *  T_m ]

H₁ = Hit rate of level 1 cache = 0.7
T₁ = Access time for level 1 cache = 0.5 ns
H₂ = Hit rate of level 2 cache = 0.8
T₂ = Access time for level 2 cache = 5 ns
H_m = Hit rate of Main Memory = 1
T_m = Access time for Main Memory = 100 ns

Average Access time =0.7*0.5 + 0.3 *(0.8)*(5)+ 0.3*(0.2)*(100)
So, Average Access time 7.55 ns

• The NEG instruction negates a value by finding 2's complement of its single operand.
• This simply means multiply operand by -1.
• When a positive value is negated the result is negative.
• A negative value will become positive.

MOV AL, 153 // load 153 to accumulator
NEG AL   //  Now Accumulator have -153

153 = 1001 1001
its 2's compliment is 0110 0111
NEG(153) = -153(  1111 1111  0110 0111)

AL = 0110 0111  // -153
Status of Carry Flag (CF) = 0 // we don't have any carry
Sign Flag (SF) = 1 // -153 negative number

So, option(B) is the Correct Answer

• Self reallocating code required for Displacement Addressing Mode. Auto Increment is useful for Array implementation
• In Auto increment/decrement Addressing Mode , Register will be automatically incremented or decremented So, ALU is required. But additional ALU is not required.
• For incrementing the data, the auto-increment addressing mode is used which purely depends on the size of the data.  In Auto increment mode automatically increments the contents of a register by a value that corresponds to the size of the accessed operand. Thus , the increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit operands. The size of the operand is usually specified as part of the operation code of an instruction.

Drum rotating at 4000 revolutions per minute

• 4000 revolutions = 1 minute
• 4000 revolutions = 60 seconds

1 revolution takes = 60/4000 seconds

Average Access Time is time to complete 1/2 revolution = 7.5 ms

option(B) printing mistake : T1>=T2

• Pipelining does not increase the execution time of a single instruction.
• Pipelining is one way of improving the overall processing performance of a processor.
• Pipelining increases the overall performance by splitting the execution to multiple pipeline stages so that the following instructions can use the finished stages of the previous instructions
• Pipelining architectural approach allows the simultaneous execution of several instructions

Assume that each stage takes ‘T’ unit of time both in pipelined and non-pipelined CPU.
Let total stages in pipelined CPU = Total stages in non-pipelined CPU = K
Number of Instructions = N = 1

• Pipelined CPU = Total time (T1) = (K + (N – 1)) * T = KT
• Non-Pipelined CPU = Total time (T2) = KNT = KT
• Considering buffer delays in pipelined CPU= T1 >= T2

Dynamic memory refreshes periodically due to this refreshment it is difficult to interface processor

Memory access time

• Access time is the amount of time it takes the processor to read data, instructions, and information from memory.

Memory Cycle Time

• It is the time that is measured in nanoseconds, the time between one Ram access of time when the next Random Access Memory RAM access starts
• Cycle time representing the minimum time interval between two successive accesses

• Size of each Ram chip = 8K x 4 bits = 2³ x 2¹⁰ x 2²  = 2¹⁵ bits
• This is bye addressable each address space represents one byte of storage space  (2¹⁵)/8 Byte =2¹²  Bytes
• Number of chips required = 6 x 4 = 24 = 5 bits required to represent 24 chips
• So, Total number of bits required = 12 + 5 = 17 bits

As the page size is 2¹³ Bytes and page coloring is asked so we divide cache size by page
size and group 16 pages in one set.
Number of pages in cache = 1MB/8KB = 128 pages
Number of set in cache=128/16=8 sets
Take any page of LAS, it will be mapped with cache on any one of these 8 sets (set association mapping).
For any two synonym to map with same set they should be colored with same color of that respective set.
So minimum we need 8 colors for this mapping.

SSTF : (90) 120 115 110 130 80 70 30 25 20
Direction changes at 120,110,130
Total 3 changes in SSTF

FCFS : (90) 120 30 70 115 130 110 80 20 25
Direction changes at 120,30,130,20
Total 4 changes in FCFS

The first element of a machine level instruction is almost always a fixed length collection of bits containing a code that identifies the specific operation to be performed While not all possible bit patterns that could appearin this operation code (or op code) field need necessarily be valid operation identifiers, the number of possible bit patterns provides an upper limit for the number of operations that the processor could support. For example, an 8-bit op code would limit a processor to a maximum of 256 different operations.

• During context switch between processes , the state of the first process must be saved so that, when the scheduler gets back to the execution of the first process, it can restore this state and continue. PC, stack and registers must be saved as otherwise program cannot resume.
•  Translation lookaside buffer (TLB) is a CPU cache that memory management hardware uses to improve virtual address translation speed. They are just bonus for ensuring better performance. We don’t need to save TLB to ensure correct program resumption.

In 8085  Accumulator is an 8-bit register i.e,. it can store 8-bit of data. Accumulator is the part of the arithmetic and logical unit (ALU). After performing arithmetical or logical operations, the result is stored in accumulator.
Accumulator is also defined as register A .
In other word Accumulator is a register in which intermediate arithmetic and logic results are stored

64 bits

Given, total number of instructions (n) = 100

For naive pipeline (NP):
Number of stages(k) = 5
Clock time (Tp) = max { (stage delay+buffer delay) } = {15 , 8, 25, 4, 8} + 5 = 30 nsec
Execution time (Enp) = ( k + n - 1 )*Tp = ( 5 + 100 - 1 )*30 = 3120 nsec

For efficient pipeline (EP):
Number of stages(k) = 7 ( delay with 25 nsec stage is divided into 12 nsec,5 nsec and 8 nsec )
Clock time (Tp) = max { (stage delay+buffer delay) } = {15 , 8, 12, 5, 8, 4, 8} + 5 = 20 nsec
Execution time (Eep) = ( k + n - 1 )*Tp = ( 7 + 100 - 1 )*20 = 2120 nsec

Speedup = (Enp) / (Eep) = 3120 / 2120 = 1.471

There used to be a time, when every track of a hard disk had the same number of sectors with the same number of bits in them. Which meant, that the bit density in the inner tracks was much higher than in the outer sectors.

(Bits Per Inch) The measurement of the number of bits stored in one linear inch of a track (storage channel) on a disk or tape.

• Pointers require indirect addressing mode.
• Arrays required indexing modes.
• An array and record access needs a pointer access. So, options (A), (B) and (C) cannot be implemented on such a processor

8192*8 means that you have:

• 8192 locations
• 8 bits per location

It means that a memory of 8192 words, where each word is 8 bits.
So to address 8192   we need 13 bits (2¹³=8192),
so 13 address lines.

The Program Counter (PC) register keeps track of the execution of the program. It contains the memory address of the instruction currently being executed . During the execution of the current instruction, the contents of the PC are updated to correspond to the address of the next instructions to be executed.

MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. MAR, which is found inside the CPU, goes either to the RAM (random access memory) or cache.

The memory address register is half of a minimal interface between a microprogram and computer storage; the other half is a memory data register.

In general, MAR is a parallel load register that contains the next memory address to be manipulated. For example, the next address to be read or written.

Reference : https://en.wikipedia.org/wiki/Memory_address_register

In register addressing mode the operand is held in memory. The address of the operand location is held in a register which is specified in instruction.
Point To Note : Generally 4 types of Instructions are there
PUSH A : Direct
PUSH B : Register
Add : Register Indirect
Pop.C : Immediate

• The NEG instruction negates a value by finding 2's complement of its single operand.
• This simply means multiply operand by -1.
• When a positive value is negated the result is negative.
• A negative value will become positive.

MOV AL, 153 // load 153 to accumulator
NEG AL   //  Now Accumulator have -153

153 = 1001 1001
its 2's compliment is 0110 0111
NEG(153) = -153(  1111 1111  0110 0111)

AL = 0110 0111  // -153
Status of Carry Flag (CF) = 0 // we don't have any carry
Sign Flag (SF) = 1 // -153 negative number

So, option(B) is the Correct Answer

• Self reallocating code required for Displacement Addressing Mode. Auto Increment is useful for Array implementation
• In Auto increment/decrement Addressing Mode , Register will be automatically incremented or decremented So, ALU is required. But additional ALU is not required.
• For incrementing the data, the auto-increment addressing mode is used which purely depends on the size of the data.  In Auto increment mode automatically increments the contents of a register by a value that corresponds to the size of the accessed operand. Thus , the increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit operands. The size of the operand is usually specified as part of the operation code of an instruction.

Total Number of tasks  n = 100
Time taken by non pipeline Tn to process a task = 50 ns

NON-Pipeline
Time period of 100 tasks  =  (Number of tasks)  * (Time taken for process each task)
Time period of 100 tasks  = n*T_n
Time period of 100 tasks  = 100 x 50 = 5000 ns

With PipeLined
Number of segment pipeline "K" = 6
Time period of 1 clock cycle  = 10 ns
Total time required = ( k + n - 1)tp
Total time required= ( 6 + 100 - 1)10
Total time required= 1050 ns

Speed up ratio " S" = 5000/1050
Speed up ratio " S"= 4.76

The Principle of Locality of Reference justifies the use of cache Memory.
In other words, Locality of Reference refers to the tendency of the computer program to access instructions whose addresses are near one another.

locality of reference. There are two ways with which data or instruction is fetched from main memory and get stored in cache memory. These two ways are the following:

Temporal Locality :
Temporal locality means current data or instruction that is being fetched may be needed soon.
In Temporal Locality The Least Recently Algorithm is Used (LRU)
Clustering in time: items referenced in the immediate past have a high probability of being re-referenced in the immediate future

Spatial Locality:
Spatial locality means instruction or data near to the current memory location that is being fetched, may be needed soon in the near future.
Clustering in space: items located physically near an item referenced in the immediate past have a high probability of being re-referenced in the immediate future  

Refer : https://www.cs.usask.ca/faculty/bunt/presentations/Locality.ppt 

• Internal Interrupt :- Interrupt which arises from illegal or erroneous use of an instruction or data. Eg. :- Register overflow, stack overflow, Protection violation.
• External Interrupt :- Hardware error like power failure, memory parity error, I/O controller, Timer( internal processor timer is used in pre-emptive multi-tasking)
• Hardware Interrupt :- Interrupt generated by hardware. Eg. :- temperature sensor etc.
• Software Interrupt :- System calls intentionally written by programmer
• Asynchronous Interrupt :- If the interrupts are independent or not in phase to the system clock is called asynchronous interrupt.
• Periodic Interrupt :- If the interrupts occurred at fixed interval in timeline then that interrupts are called periodic interrupts.
• Synchronous Interrupt :- The interrupt which are dependent on the system clock. Eg. :- Timer service
• Nested Interrupt :- If an interrupt occurs while executing a program, and the processor is executing the interrupt, if one more interrupt occurs again, then it is called a nested interrupt.

• Swap space  is used when the amount of physical memory (RAM) is full. If the system needs more memory resources and the RAM is full, inactive pages in memory are moved to the swap space.
• While swap space can help machines with a small amount of RAM, it should not be considered a replacement for more RAM.
• Swap space is located on hard drives(Disk or any)

• Direct Addressing Mode Effective address of operand is present in instruction itself.
• Single memory reference to access data.
• No additional calculations to find the effective address of the operand.
• Usually indicated by variable names

Refer for More information : 
https://www.studytonight.com/computer-architecture/addressingmodes-instructioncycle#:~:text=Direct%20Addressing%20Mode&text=For%20Example%3A%20ADD%20R1%2C%204000,location%20where%20operand%20is%20present.

Polling vs Interrupts I/O
A computer must have a way of detecting the arrival of any type of input. There are two ways that this can happen, known as polling and interrupts. Both of these techniques allow the processor to deal with events that can happen at any time and that are not related to the process it is currently running.

Polling I/O
Polling is the simplest way for an I/O device to communicate with the processor. The process of periodically checking status of the device to see if it is time for the next I/O operation, is called polling. The I/O device simply puts the information in a Status register, and the processor must come and get the information.

Most of the time, devices will not require attention and when one does it will have to wait until it is next interrogated by the polling program. This is an inefficient method and much of the processors time is wasted on unnecessary polls.

Compare this method to a teacher continually asking every student in a class, one after another, if they need help. Obviously the more efficient method would be for a student to inform the teacher whenever they require assistance.
Reference :
https://www.tutorialspoint.com/operating_system/os_io_hardware.htm#:~:text=The%20process%20of%20periodically%20checking,O%20operation%2C%20is%20called%20polling.

Central processing unit (CPU), principal part of any digital computer system, generally composed of the main memory, control unit, and arithmetic-logic unit.

The time to transfer 250 bytes from the disk equals =
Average seek time + the average rotational latency + the transfer time for 250 bytes

The Average seek time equals:
Given that :
time to move between successive tracks is 1 ms
time to move from track 1 to track 1: 0ms
time to move from track 1 to track 2: 1ms
time to move from track 1 to track 3: 2ms
..
..
time to move from track 1 to track 500 :  499m
Avg Seek time = ( ∑0+1+2+3+…+499)/500 = 249.5 ms

Avg Rotational Delay

• Rotation speed = 600 RPM.
• 600 rotations  =   60 sec
• 1 rotation   =  60/600  sec= 0.1 sec

So, Avg Rotational Delay = 0.1/2=  =0.05 sec = 50 ms

Data Transfer Time: 
In 1 Rotation we can read data on 1 complete track  =
100×500 = 50,000 Bytes data is read in one complete rotation
1 complete rotation takes 0.1 s
0.1 → 50,000 bytes.
250 bytes →0.1×250 / 50,000 = 0.5 ms
Data Transfer Time = 0.5 ms

Avg. time to transfer = Avg. seek time + Avg. rotational delay + Data transfer time
Avg. time to transfer= 249.5+50+0.5
Avg. time to transfer= 300 ms

In synchronous mode of transfer we don’t require start and stop bits

• Total number of bits per character while transmitting is (7+1)=8 bits
• No of character transmitted 2400/8=300 bps

In Asynchronous transfer, we need start and stop bits in order to synchronize these bits are added to the number of bits in each character.

• Total number of bits per character while transmitting is (7+1+1+1)=10 bits
• No of character transmitted 2400/10=240 bps

 

In One-address instructions, an accumulator register is required

• Accumulator CPU is  an example of One Address Instruction
• Load and store operations are performed to fetch the values of operands from registers or memory to accumulators and to store the value of accumulator to a memory location.

X = (M + N * O) / (P * Q)

1. Load A : ACC <-- M[M]                 //Load M value from memory  to ACCUMULATOR
2. Add N : ACC <-- ACC + M[N]     //ADD N value  to ACCUMULATOR and store Results in ACCUMULATOR
3. Mul O : ACC <-- ACC x M[O]      // Multiply O value  to ACCUMULATOR and store Results in ACCUMULATOR
4. Store T : M[T] <-- ACC              //  Now Store Results in Memory
5. Load P : ACC <-- M[P]                // Load P value from memory  to ACCUMULATOR
6. Mul Q : ACC <-- ACC x M[Q]   // Multiply Q value  to ACCUMULATOR and store Results in ACCUMULATOR
7. Div T : ACC <-- M[T] / ACC     // devide memory value(step4) with ACCUMULATOR and store Results in Acc
8. Store X : M[X] <-- ACC           // store Accumulator results in Memory

• Cycle time is the minimum time delay between the initiations of two independent memory operations.
• The Time taken by the cpu to end one read operation and to start one more is cycle time.

Contribute your solution in Discussion Forum
Discussion Forum     

A load word or store word instruction uses only one memory address. The lowest address of the four bytes is used for the address of a block of four contiguous bytes.

How is a 32-bit pattern held in the four bytes of memory? There are 32 bits in the four bytes and 32 bits in the pattern, but a choice has to be made about which byte of memory gets what part of the pattern. There are two ways that computers commonly do this:

Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.

Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.

In these definitions, the data, a 32-bit pattern, is regarded as a 32-bit unsigned integer. The "most significant" byte is the one for the largest powers of two: 2³¹, ..., 2²⁴. The "least significant" byte is the one for the smallest powers of two: 2⁷, ..., 2⁰.

For example, say that the 32-bit pattern 0x12345678 is stored at address 0x00400000. The most significant byte is 0x12; the least significant is 0x78.

Within a byte the order of the bits is the same for all computers (no matter how the bytes themselves are arranged).



Source :  https://chortle.ccsu.edu/AssemblyTutorial/Chapter-15/ass15_3.html#:~:text=The%20%22least%20significant%22%20byte%20is,the%20least%20significant%20is%200x78. 

ADD r1, r2, (r3)
Require two memory accesses, the first to read the instruction and the other
one to read the value from memory location(s), whose address is in r3

• Instruction Cache  :  Used for storing frequently used instructions
• Instruction Register  :  Part of CPU’s control unit that stores the instruction currently being executed
• Instruction Opcode : The instruction opcode is a part of the instruction which tells the processor what operation is to be performed so it is not a form of memory while the others are instruction cache, instruction register and translation look a side buffer are the forms of memory
• Translation Lookaside Buffer : It is a memory cache that stores recent translations of virtual memory to physical addresses for faster access.

Speedup factor S=10
Efficiency e= 80%= 0.8

Efficiency e= (Speedup factor s) / (Number of stages k)

• e= S/k
• k= S/e
• K=S/e=10/0.8=12.5  ≏ 13 stages

No of Stages  = 13

RAID level 1 refers to disk mirroring with block striping.

• RAID 0 (also known as a stripe set or striped volume) splits ("stripes") data evenly across two or more disks, without parity information, redundancy, or fault tolerance.
• RAID 1 consists of an exact copy (or mirror) of a set of data on two or more disks; a classic RAID 1 mirrored pair contains two disks
• RAID 2, which is rarely used in practice, stripes data at the bit (rather than block) level, and uses a Hamming code for error correction.
• RAID 3, which is rarely used in practice, consists of byte-level striping with a dedicated parity disk.
• RAID 4 consists of block-level striping with a dedicated parity disk.
• RAID 5 consists of block-level striping with distributed parity. Unlike in RAID 4, parity information is distributed among the drives. It requires that all drives but one be present to operate
• RAID 6 extends RAID 5 by adding another parity block; thus, it uses block-level striping with two parity blocks distributed across all member disks

• Number of possible instruction encoding =2¹⁰=1024
• Number of encoding taken by Two-address instructions = 4×2³×2³=4*8*8= 256
• Number of encoding taken by One-address instructions =16×2³=16*8=128
• So, Number of possible Zero-address instructions =1024− (256 + 128)=640

• zero-address instruction An instruction that contains no address fields; operand sources and destination are both implicit. It may for example enable stack processing: a zero-address instruction implies that the absolute address of the operand is held in a special register that is automatically incremented (or decremented) to point to the location of the top
• One-address instructions use an implied accumulator (AC) register for all data manipulation. For multiplication and division there is a need for a second register. However, here we will neglect the second and assume that the AC contains the result of tall operations.
• In Two address instruction each address field can specify either a processor register or a memory word.
• In three-address instruction each address field to specify either a processor register or a memory operand.

They are asking about SET INDEX
"SET INDEX" is referred as SET OFFSET.

• In fully Associative only 1 set so SET INDEX not exit
• In Set-Associative if you have s sets then SET INDEX will be log₂ s

It means we require log₂ s bits  in order to represent s sets in  K-way set Associative

Source : https://www.iare.ac.in/sites/default/files/PPT/CO%20Lecture%20Notes.pdf

Given

•  Number of stages : 6
• Time taken for each stage : 20ns, 10ns, 30ns,25ns, 40 ns 15ns

Without pipeline
Execution time  1 instruction = 20ns+10ns+30ns+25ns+40ns+15ns  =140ns

With pipeline
Implementing pipeline adds 5 ns of overhead to each stage
So Add 5 ns  to each stage
With ideal pipeline it will take 1 cycle time. Here 1 cycle time is max(25, 15, 35, 30, 45, 20) = 45ns

Speedup = ( Time without pipelining )  / ( Time with pipelining )
Speedup = 140/45= 3.11

CISC	RISC
Focus on software	Focus on hardware
Uses only Hardwired control unit	Uses both hardwired and micro programmed control unit
Transistors are used for more registers	Transistors are used for storing complex Instructions
Fixed sized instructions	Variable sized instructions
Can perform only Register to Register Arthmetic operations	Can perform REG to REG or REG to MEM or MEM to MEM
Requires more number of registers	Requires less number of registers
Code size is large	Code size is small
A instruction execute in single clock cycle	Instruction take more than one clock cycle
A instruction fit in one word	Instruction are larger than size of one word
A large number of instructions are present in the architecture.	Very fewer instructions are present. The number of instructions are generally less than 100.
Some instructions with long execution times. These include instructions that copy an entire block from one part of memory to another and others that copy multiple registers to and from memory.	No instruction with a long execution time due to very simple instruction set. Some early RISC machines did not even have an integer multiply instruction, requiring compilers to implement multiplication as a sequence of additions.
Variable-length encodings of the instructions. Example: IA32 instruction size can range from 1 to 15 bytes.	Fixed-length encodings of the instructions are used. Example: In IA32, generally all instructions are encoded as 4 bytes.
Multiple formats are supported for specifying operands. A memory operand specifier can have many different combinations of displacement, base and index registers.	Simple addressing formats are supported. Only base and displacement addressing is allowed.
CISC supports array.	RISC does not supports array.
Arithmetic and logical operations can be applied to both memory and register operands.	Arithmetic and logical operations only use register operands. Memory referencing is only allowed by load and store instructions, i.e. reading from memory into a register and writing from a register to memory respectively.
Implementation programs are hidden from machine level programs. The ISA provides a clean abstraction between programs and how they get executed.	Implementation programs exposed to machine level programs. Few RISC machines do not allow specific instruction sequences.
Condition codes are used.	No condition codes are used.
The stack is being used for procedure arguments and return addresses.	Registers are being used for procedure arguments and return addresses. Memory references can be avoided by some procedures.

Refer : https://onlinelibrary.wiley.com/doi/pdf/10.1002/0471741973.app2#:~:text=Implied%20addressing%20refers%20to%20instructions,%E2%80%9Cincrement%20accumulator%E2%80%9D)%20instruction.&text=Recognizing%20that%20this%20is%20an,on%20to%20the%20next%20instruction.

• S1: Interpreters process program according to the logical flow of control through the program.  TRUE
• S2: Interpreters translates and executes the error-free first instruction before it goes to the second. TRUE Interpreter goes line-by-line of the program & executes line by line.
• S3: Interpreter processing time is less compared with compiler. FALSE
  Because Compiler processing time is FASTER than Interpreter.
• S4: LISP and Prolog are interpreted languages. TRUE Prolog is written to work with Microsoft Windows and is a Compiler version; however, they offer a sample program called ‘PIE', which is a simplified Prolog Interpreter
•  So, option (D) Only S1, S2 and S4 is CORRECT

Software interrupts: It is initiated by executing an instruction. These are special call instructions that behaves like an interrupt rather than subroutine call. These can be used by the programmer to initiate an interrupt procedure at any designed point of the program. These interrupts arc usually used for switching to supervisor made from user mode.

CALL instruction is used whenever we need to make a call to some procedure or a subprogram. Whenever a CALL is made, the following process takes place inside the microprocessor:

• The address of the next instruction that exists in the caller program (after the program CALL instruction) is stored in the stack.
• The instruction queue is emptied for accommodating the instructions of the procedure.

microprogram
The computer understands only binary language. So, the microprogram should have instructions which are in the form of 0s and 1s. Each output line of the micro-program corresponds to one control signal.

Reference : https://www.includehelp.com/embedded-system/the-call-and-ret-instruction-in-the-8086-microprocessor.aspx#:~:text=The%20CALL%20instruction%20in%20the%208086%20microprocessor&text=The%20address%20of%20the%20next,the%20instructions%20of%20the%20procedure.

• In General, if the branch instruction is known at Nth stage then the number of stalls would be =  (N - 1)
• Here Given  N =5
• Number of stalls = (N-1)=(5-1) = 4 Stall Cycles