## Analog Circuits Subject WIse

Question 1 |

_{s}is a square wave of period T with maximum and minimum values of 8 V and -10 V, respectively. Assume that the diode is ideal and R

_{1}= R

_{2}= 50 Ω.

The average value of V

_{L}is _________ volts (rounded off to 1 decimal place).

Fill in the Blank Type Question |

Question 2 |

_{tp}|) and nMOS (V

_{tn}) transistors are both equal to 1 V. All the transistors have the same output resistance r

_{ds}of 6 MΩ. The other parameters are listed below.

Μ_{n} and μ_{p} are the carrier mobilites, and C_{ox} is the oxide capacitance per unit area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is ____________(rounded off to 1 decimal place).

Fill in the Blank Type Question |

Question 3 |

acceptor concentration NA = 5 × 10

^{16}cm

^{-3},

electron mobility μ

_{n}= 800 cm

^{2}/V-s,

oxide capacitance/area C

_{ox}= 3.45 × 10

^{-7}F/cm

^{2},

threshold voltage V

_{T}= 0.7 V.

The drain saturation current (I

_{Dsat}) for a gate voltage of 5 V is ____________ mA (rouonded off to two decimal places).

[ε_{0} = 8.854 × 10^{-14} F/cm, ε_{si} = 11.9]

Fill in the Blank Type Question |

Question 4 |

_{1}= 0 and V

_{2}= V

_{dd}. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of I

_{out}is ___________ mA (rounded off to 1 decimal place).

Fill in the Blank Type Question |

Question 5 |

_{I}equal to half of V

_{dd}, as shown in the figure, has the following parameters :

V_{dd} = 3 V

μ_{n}C_{ox} = 100 μA/V^{2} ; V_{tn} = 0.7 V for nMOS

μ_{n}C_{ox} = 40 μA/V^{2} ; |V_{tp}| = 0.9 V for pMOS

The ratio of to is equal to __________ (rounded off to 3 decimal places).

Fill in the Blank Type Question |

Question 6 |

_{s}is a 10 V square wave of period, T = 4 ms with R = 500 Ω and C = 10 μF. The capacitor is initially uncharged at t = 0, and the diode is assumed to be ideal. The voltage across the capacitor (V

_{c}) at 3 ms is equal to ________ volts (rounded off to one decimal place).

Fill in the Blank Type Question |

Question 7 |

_{1}and R

_{L}are 200 Ω and 1 kΩ, respectively. What is the range of V

_{i}that will maintain the Zener diode in the ‘on’ state?

18 V to 24 V | |

20 V to 28 V | |

24 V to 36 V | |

22 V to 34 V |

Question 8 |

+5V and -5V | |

+7V and -3V | |

+3V and -7V | |

+3V and -3V |

Question 9 |

High input impedance and low output impedance | |

Low input impedance and high output impedance | |

High input and output impedances | |

Low input and output impedances |

**->**A good transconductance amplifier has current as output and voltage as input that means it should have high input and high output impedances.

**->**A good trans conductance amplifier should have high input and output resistance

Question 10 |

The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain, and an open-loop cut-off frequency, f_{c}= 8 Hz. The voltage gain of the amplifier at 15kHz, in V/V, is ______.

Fill in the Blank Type Question |

Question 11 |

low input impedance and high output impedance | |

high input impedance and high output impedance | |

high input impedance and low output impedance | |

low input impedance and low output impedance |

Question 12 |

The time in milliseconds, at which the output voltage crosses – 10 V is

2.5 | |

5 | |

7.5 | |

10 |

Question 13 |

For the amplitude of the small-signal component of diode current (in μA, correct to one decimal place) is ___________.

Fill in the Blank Type Question |

Question 14 |

In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place) at node A, connected to the negative input of the op-amp as indicated in the figure is ___________.

Fill in the Blank Type Question |

Question 15 |

The value of R and the minimum required power dissipation rating of the diode, respectively, are

Question 16 |

_{GS}>V

_{TH }and, V

_{DS}>(V

_{GS}-V

_{TH}), where V

_{GS}is the gate-to-source voltage, V

_{DS }is the drain-to-source voltage and V

_{TH }is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves like a

Voltage source with zero output impedance | |

Voltage source with non-zero output impedance | |

Current source with finite output impedance | |

Current source with infinite output impedance |

and it can be used as an amplifier.

So it can act as current source with finite output impedance.

**Hence Option(c) is correct**

Question 17 |

Assuming 10 τ <<T. where τ is the time constant of the circuit, the maximum and minimum values of the output waveform are respectively.

7.5 V and –20.5V | |

6.1 V and –21.9V | |

7.5 V and –21.2 V | |

6.1 V and –22.6 V |

Question 18 |

_{1}and T

_{2}, are identical in all respects except that the width of T

_{2}is double that of T

_{1}. Both the transistors are biased in the saturation region of operation, but the gate overdrive voltage (V

_{GS}-V

_{TH}) of T

_{2}is double that of T

_{1}, where V

_{GS}and V

_{TH}are the gate – to – source voltage and threshold voltage of the transistors, respectively. If the drain current and transconductance of T

_{1}are ID

_{1}and gm

_{1}respectively, the corresponding values of these two parameters for T

_{2}are

Question 19 |

_{0}/V

_{s}in the mid-band frequency range is __________ (up to second decimal place).

Fill in the Blank Type Question |

Question 20 |

Voltage at emitter of PNP BJT

The current through R

Question 21 |

Fill in the Blank Type Question |

LED will glow when V

_{i}> 2 V

Here V

_{i}crosses 2 V, 3 times

Therefore LED glows 3 times

**Correct Answer is 3**

Question 22 |

Introduce amplitude stabilization by preventing the op amp from saturating and thus producing sinusoidal oscillations of fixed amplitude | |

Introduce amplitude stabilization by forcing the op-amp to swing between positive and negative saturation and thus producing square wave oscillations of fixed amplitude | |

Introduce frequency stabilization by forcing the circuit to oscillate at a single frequency | |

Enable the loop gain to take on a value that produces square wave oscillations |

Question 23 |

10 kHz, 20 kHz, 40 kHz, 80 kHz | |

20 kHz, 40 kHz, 80 kHz, 160 kHz | |

80 kHz, 40 kHz, 20 kHz, 10 kHz | |

160 kHz, 80 kHz, 40 kHz, 20 kHz |

Question 24 |

OV | |

Switching threshold of inverter | |

V _{DD} |

Since the inverter is connected in feedback loop formed by connecting 1OXQ resistor between the output and input, the output goes and stays at the middle of the characteristics

Switching threshold of inverter

Question 25 |

_{1}, V

_{3}, V

_{5}, ..., V

_{N-1}connected to the non-inverting input and V

_{2},V

_{4}, V

_{6}, ..., V

_{N}connected to the inverting input as shown in the figure below (+V

_{cc}= 15 volt,—V

_{cc}= —15 volt). The voltages V

_{1}, V

_{2}, V

_{3}, V

_{4}, V

_{5,}V

_{6},... are 1, — 1/2, 1/3, —1/4, 1/5, —1/6,... volt, respectively. As N approaches infinity, the output voltage (in volt) is

Fill in the Blank Type Question |

Question 26 |

_{out}) for the given sine wave input (υ

_{in}) will be

During positive pulse, both diodes are forward biased.

During negative pulse, both diodes are reverse biased.

So, V

_{o}= 0V

Hence, the correct option is (C).

Question 27 |

_{DS}= 0.5 V. If the channel length modulation coefficient is 0.05 V

^{–1}, the output resistance (in kΩ) of the MOSFET is _______.

Fill in the Blank Type Question |

Question 28 |

_{th}, where V

_{th}> 0. The source voltage V

_{SS}is varied from 0 to V

_{DD}. Neglecting the channel length modulation, the drain current I

_{D}as a function of V

_{SS}is represented by

Hence MOS transistor is in saturation.

In saturation,

As V

_{ss}increases I

_{D}decreases (Not linearly because square factor)

Hence option A. is correct.

Question 29 |

Question 30 |

The magnitude of the current i

_{2}(in mA) is equal to _____.

Fill in the Blank Type Question |

net current I=2/(6+2)=0.25mA

so voltage drop across diode=0.25*2=0.5V

our assumption of diode is off is correct

so current will be

I

_{2}= 2/8k = 0.25mA

Question 31 |

_{1}in the circuit below figure has been adjusted so that I

_{1}= 1 mA. The bipolar transistors Q

_{1}and Q

_{2}are perfectly matched and have very high current gain, so their base currents are negligible. The supply voltage V

_{cc}is 6 V. The thermal voltage kT/q is

26 mV.

The value of R

_{2 }(in ohms)

_{ }for which I

_{2 }=100μA is...........

Fill in the Blank Type Question |

,.....................(i)

,........................(ii)

from equation (i) & (ii),

Question 32 |

The device parasitic capacitances behave like open circuits, whereas coupling and by pass capacitances behave like short circuits. | |

The device parasitic capacitances, coupling capacitances and bypass capacitances behave like open circuits. | |

The device parasitic capacitances, coupling capacitances and bypass capacitances behave like short circuits. | |

The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances behave like open circuits. |

Question 33 |

_{o}= 1 A from the rectifier. The figure also shows the input voltage V

_{i}, the output voltage V

_{c}and the peak-to-peak voltage ripple u on V

_{c}. The input voltage V

_{1}is a triangle-wave with an amplitude of 10 V and a period of 1ms The value of the ripple u (in volts) is ____

Fill in the Blank Type Question |

V

_{ripple}= 2.1 Volts

Question 34 |

_{1}and Z

_{2}clamp the output voltage V

_{o}to +5 V or -5V. The switch S is initially closed and is opened at time t=0 The time t = t

_{1}(in seconds) at which V

_{o}changes state is ____

Fill in the Blank Type Question |

Question 35 |

**V**is modeled as shown in the circuit below. The amplifier is ideal in all other respects.

_{ios}(= +5 mV)**V**Is

_{input}**25 mV**

The output voltage (in millivolts) is _____

Fill in the Blank Type Question |

Question 36 |

Fill in the Blank Type Question |

Question 37 |

Fill in the Blank Type Question |

Question 38 |

Fill in the Blank Type Question |

The overall voltage gain

Question 39 |

Question 40 |

**g**. Ignoring internal parasitic capacitances and assuming the channel length modulation to be zero, the small signal input pole frequency (in kHz) is.

_{m}= 0.01 siemensFill in the Blank Type Question |

Question 41 |

Fill in the Blank Type Question |

Question 42 |

_{s}= 10

^{–15}A is biased in the forward active region with V

_{BE}= 700 mV. The thermal voltage (V

_{T}) is 25 mV and the current gain (b) may vary from 50 to 150 due to manufacturing variations. The maximum emitter current (in mA) is___.

Fill in the Blank Type Question |

Question 43 |

_{0}/ v

_{in}) is –12, the value of R (in kΩ) is _____.

Fill in the Blank Type Question |

Given

Question 44 |

_{1}and D

_{2}are ideal. The average value of voltage V

_{ab}(in volts), across terminals ‘a’ and ‘b’ is ________.

Fill in the Blank Type Question |

Question 45 |

RC << T | |

RC = 0.35T | |

RC T | |

RC >> T |

**->**Time constant = t = RC

If RC >> T = period of sinusoid

Then the capacitor will not play its role i.e. it will not discharge and clamping will take place.

**->**For an ideal clamping circuit once the capacitor is charged it should not discharge. Hence discharging time constant (RC) must be much larger than the time period of input signal. i.e. RC >> T

Question 46 |

_{0}= V

_{0A}for switch SW in position A and V

_{0}= V

_{0B}for SW in position B. Assume that the opamp is ideal. The value of is _____________

1.5 | |

4 | |

10 | |

15 |

Hence V

_{OB}/ V

_{OA}= -6/-5= 6/5 =

**1.5**

Question 47 |

1 | |

-1 | |

0 | |

2 |

Question 48 |

_{ON}= 0.7 V but is ideal otherwise. The current (in mA) in the 4kΩ resistor is______ mA

0.6 | |

1.6 | |

1.5 | |

4 |

Question 49 |

a decrease in the threshold voltage | |

channel length modulation | |

an increase in substrate leakage current | |

an increase in accumulation capacitance |

V

_{TH}= V

_{FB}- Q

_{ox}/C

_{ox}Therefore, threshold voltage decreases.

Question 50 |

Low input impedance and low output impedance | |

Low input impedance and high output impedance | |

High input impedance and low output impedance | |

High input impedance and high output impedance |

So, a good currrent buffer should have low input impedance and high output impedance.

Question 51 |

_{in}is the input current and R

_{F}is very large, the type of feedback is

voltage-voltage feedback | |

voltage-current feedback | |

current-voltage feedback | |

current-current feedback |

Since, feedback is diectly connected to output so the sampling is voltage and mixing is current type.

∴ It is voltage – shunt negative feedback i.e., voltage-current negative feedback

Question 52 |

_{2}(in ) is ____________.

2.24 | |

2.82 | |

3.18 | |

3.42 |

Question 53 |

4 V, 3 V, 2 V | |

5 V, 5 V, 5 V | |

4 V, 4 V, 4 V | |

5 V, 4 V, 3 V |

Question 54 |

4.425 | |

4.475 | |

5.525 | |

5.785 |

Question 55 |

**V**and the zener voltage is 4.7V. For a regulated output of 9 V, the value of R(inW) is ______ .

_{BE}= 0.7V and β = 100,893 | |

993 | |

1093 | |

1193 |

Question 56 |

_{out}is

_{i}= finite

A = ∞

V

_{2}= (R

_{1}||R

_{2})I

_{1}=

KCL at inverting node

Question 57 |

**V**and thermal voltage

_{BE}= 0.7V and β = 200,**V**The voltage gain

_{T}= 25mV**( V**of the amplifier is _______

_{o}/ V_{i})137.76 | |

-137.76 | |

237.76 | |

-237.76 |

Question 58 |

The common emitter dc current gain decreases | |

the breakdown voltage | |

the unity-gain cut-off frequency f _{T} | |

the trans conductance g _{m} |

Question 59 |

low pressure chemical vapour deposition | |

low energy sputtering | |

low temperature dry oxidation | |

low energy ion-implantation |

- In CMOS, an n-well is used to fabricate PMOS if the substrate is p-type.
- In CMOS, p-well is used to fabricate NMOS if the substrate is n-type.
- For n-well CMOS process, an initial thick oxide layer (5000 A
^{o}) is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms usually phosphorous are implanted through this window in the oxide.

Question 60 |

Voltage shunt feedback | |

Current series feedback | |

Current shunt feedback | |

Voltage series feedback |

_{f}is subtracted from the signal same v

_{s}it is series mixing.

Question 61 |

_{cm}and A

_{d}, respectively. If the resistance RE is increased, then

A _{cm} increases | |

Common-mode rejection ratio increases | |

A _{d} increases | |

Common-mode rejection ratio decreases |

_{d}does not depend on R

_{E}

A

_{cm}decreases as R

_{E}is increased

CMRR for differential amplifier is given by,

As A

_{cm}decreases CMRR increases

Question 62 |

_{v0}, input resistance R

_{in}, and output resistance R

_{O}for A1 and A2 are as follows:

The approximate overall voltage gain V

_{out}/V

_{in}is __________.

28.50 | |

32.0 | |

33.0 | |

34.722 |

Question 63 |

_{Th}is 0.8 V. Neglect channel length modulation effects. When the drain voltage V

_{D}= 1.6 V, the drain current I

_{D}was found to be 0.5 mA. If V

_{D}is adjusted to be 2 V by changing the values of R and V

_{DD}, the new value of I

_{D}(in mA) is

0.625 | |

0.75 | |

1.125 | |

1.5 |

Question 64 |

0.6 mA | |

0.7 mA | |

0.8 mA | |

0.9 mA |

Question 65 |

Isolation oxide growth | |

Channel stop implantation | |

Poly-silicon gate patterning | |

Lithography step leading to the contact pads |

Question 66 |

High input resistance and high output resistance | |

High input resistance and low output resistance | |

Low input resistance and high output resistance | |

Low input resistance and low output resistance |

Transconductance amplifier must have z

_{i}= ∞ and z

_{o}= ∞

Question 67 |

_{o}to be 5V , the value of ___________

1.075 | |

1.175 | |

2.075 | |

2.175 |

Question 68 |

0.07 | |

0.08 | |

0.09 | |

1.0 |

Question 69 |

5 Hz and 15 Hz only | |

10 Hz and 15 Hz only | |

5 Hz, 10 Hz and 15 Hz only | |

5 Hz only |

Spectrum of x(t)

Spectrum of sampled version of x(t)

After LPF, signal will contain 5 and 15Hz component only

Question 70 |

a | |

a* | |

1/a* | |

1/a |

Question 71 |

0.05 | |

0.06 | |

0.07 | |

0.08 |

Question 72 |

^{15}cm

^{-3}in the substrate. When a gate voltage is applied, a depletion region of width is formed with a surface (channel) potential of 0.2 V. Given that and the relative permittivities of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/μm) in the oxide region is __________________.

1.6 | |

2.0 | |

2.4 | |

2.8 |

Question 73 |

**β=50**Assume

**V**Which one of the following statements is correct?

_{BE}=0.7 V and V_{CE(sat)}=0.2 VFor RC = 1 the BJT operates in the saturation region | |

For RC = 3 , the BJT operates in the saturation region | |

For RC =20 , the BJT operates in the cut-off region | |

For RC =20 , the BJT operates in the linear region |

Question 74 |

_{O}is given by

Virtual ground and KCL at inverting terminal gives

Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits

Question 75 |

The transistor M

_{1}switches from saturation region to linear region when V

_{in}(in Volts) is _______

1.0 | |

1.5 | |

2.0 | |

2.5 |

Question 76 |

**4 MOSFETs are required (2-PMOS and 2-NMOS)**with interchanged outputs connected to each CMOS inverter. This condition is followed in option (B)

Question 77 |

Reduce both the voltage gain and the input impedance | |

Reduce the voltage gain and increase the input impedance | |

Increase the voltage gain and reduce the input impedance | |

Increase both the voltage gain and the input impedance |

Question 78 |

**0.7 V**, are used in the circuit shown in the figure. The range of input voltage V

_{i}for which the output voltage

**V**is

_{o}= V_{i }Question 79 |

A bandpass filter | |

A voltage controlled oscillator | |

An amplitude modulator | |

A monostable multivibrator |

A monostable multivibrator, also called a one shot, is a sequential logic electronic circuit that generates an output pulse. When triggered, a pulse of pre-defined duration is produced. The circuit then returns to its stable state and produces no more output until triggered again.

Question 80 |

Consider two BJTs biased at the same collector current with area
Assuming that all other device parameters are identical, kT/q = 26 mV, the intrinsic carrier concentration is
the difference

between the base-emitter voltages (in mV) of the two BJTs

361 | |

381 | |

412 | |

418 |

Question 81 |

Question 82 |

0.2 | |

0.4 | |

0.5 | |

0.75 |

z

_{i}= r

_{e}= V

_{I}/ I

_{E }

Question 83 |

**V**The maximum undistorted peak-to-peak output voltage V

_{CE(sat)}and V_{BE}= 0.7V_{o}(in Volts)is______.

9.6 | |

8.3 | |

8.9 | |

9.4 |

Question 84 |

_{out}) if a silicon transistor Q and an ideal op-amp are used?

15 V | |

–0.7 V | |

+0.7 V | |

+15 V |

*BJT*will be at zero voltage.

i.e.,

The current in resistor is given by

This current will flow completely through the

*BJT*since, no current will flow into the ideal op-amp (I/P resistance of ideal op-amp is infinity). So, for

*BJT*we have

i.e., the base collector junction is reverse biased (zero voltage) therefore, the collector current (IC) can have a value only if base-emitter is forward biased.

Hence,

Question 85 |

The input impedance increases and output impedance decreases. | |

The input impedance increases and output impedance also increases. | |

The input impedance decreases and output impedance also decreases. | |

The input impedance decreases and output impedance increases. |

If

*k*increased then input voltage is also increased so, the input impedance increases.

Now, we have

Since,

*V*is independent of

_{in}*k*when seen from output mode, the output voltage decreases with increase in

*k*that leads to the decrease of output impedance. Thus, input impedance increases and output impedance decreases.

Question 86 |

an increase in the gate-source capacitance | |

a decrease in the transconductance | |

a decrease in the unity-gain cutoff frequency | |

a decrease in the output resistance |

Without the channel length modulation the drain current of a MOSFET is given by,

Id = μ/2 x C(W/L)(Vgs - Vt)²

∴ dI/dV = 0

=> dV/dI = ∞

=> Rd = ∞

If we consider channel length modulation, the value of Rd will be always less than ∞ .

So, channel length modulation decreases the output resistance.

Question 87 |

_{L}, the minimum value of RL in Q and the minimum power rating of the Zener diode in mW, respectively, are

125 and 125 | |

125 and 250 | |

250 and 125 | |

250 and 250 |

Question 88 |

_{B}/dI

_{D}) in kΩ offered by the n-channel MOSFET M shown in the figure below, at a bias point of V

_{B}= 2 V is (devise data for M: device transconductance parameter , threshold voltage , and neglect body effect and channel length modulation effects)

12.5 | |

25 | |

50 | |

100 |

So, we have

Drain voltage

Therefore,

and

So, the MOSFET is in the saturation region. Therefore, drain current is

I

_{D}= 1/2 K

_{n}(V

_{GS }- V

_{T})

^{2}(Rest part i.e. 1 + λV

_{DS}is neglected as mentioned in question)

2I

_{D}= K

_{n }(V

_{B}-1)

^{2}

Differentiating both side with respect to ID

2 = K

_{n }2(V

_{B}-1)(dV

_{B}/dI

_{D)}

Since, (at D.C. Voltage)

Hence, to get small signal resistance

dV

_{B}/dI

_{D }= 2/K

_{n }2(V

_{B}-1)

= 1/40×10

^{-6}×1

= 25 KΩ

Question 89 |

_{m}= 1 mA/V. and body effect and channel length modulation effect are to be neglected. The lower cutoff frequency in Hz of the circuit is approximately at

8 | |

32 | |

50 | |

200 |

Node voltage at

*V*

_{1}as

Output voltage

*V*

_{0}is obtained as

Transfer function is

Pole at

It gives the lower cutoff frequency of transfer function.

i.e.,

or,

Question 90 |

4 | |

6 | |

8 | |

10 |

Question 91 |

sin ωt | |

(sin ωt + |sin ω t|)/2 | |

(sin ωt – |sin ω t|)/2 | |

0 for all t |

Question 92 |

_{b}through the base of a silicon npn transistor is 1 + 0.1 cos(10000 πt) mA. At 300 K, the r

_{π}in the small signal model of the transistor is

250 Ω | |

27.5 Ω | |

25 Ω | |

22.5 Ω |

_{b}= 1 + 0.1 cos(10000 πt ) mA

We know that

Where l

_{b}is d.c. current through base so

I

_{b}= 1mA

V

_{T}= 25mV at room temperature

So,

Question 93 |

C1 will be charged to maximum value of input that is 1 V.

So, according to KVL.

Question 94 |

Vin< 1.875 V | |

1.875 V < Vin< 3.125 V | |

Vin> 3.125 V | |

0 |

For PMOS to be ON

So Vin must be less than 4V for MOS to be in linear regions so option C and D are rejected. Now we know that for small Vin output is high and PMOS is in linear region and NMOS is in cutoff region. Similarly for high Vin PMOS is in cutoff and NMOS is in linear region and for Vin in between both are in saturation. So PMOS will be in linear region for Vin < 1.875 V.

Question 95 |

Low pass filter with | |

High pass filters with | |

Low pass filter with | |

High pass filter with |

T(s) =

It is the transfer function of high pass filter with cutoff frequency → ω = rad/sec

Question 96 |

Apply Miller's theorem to 100 k resistor

Question 97 |

6 V | |

7 V | |

8 V | |

9 V |

Question 98 |

165 V | |

55 V | |

220 V | |

110 V |

Here we have to find out the value of DC voltage that is being applied to the motor.

Given=> Vin=220V, Duty cycle=25%

Now, for a chopper circuit, we have:

Average output voltage=Duty cycle x Supply voltage=> (25/100) x (220)=>55. So, option (b) is the correct option.

Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits

Question 99 |

_{1}= a

_{2}= a = /2 of both transistors?

V | |

V | |

x 220 V | |

x 220 V |

Here we have to find the RMS output voltage at delay angles a

_{1}=a

_{2}=a=ᴨ/2

Now, we have a single phase full wave AC phase controller. We know the formula for Vout(Mean square value) for a AC phase controller . It is given as:

Vout(mean square)= V

_{m}/[(ᴨα)+sin2α/2]

^{(1/2)}

Here, it is already given in question that V

_{m}=220V=> 220, and α=ᴨ/2

So, putting all these values in Vout formula, we will get answer as option (a)

Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits

Question 100 |

2 diodes and 1 capacitor | |

4 diodes and 1 capacitor | |

2 diodes and 2 capacitor | |

4 diodes and 2 capacitor |

Refer : https://www.electronics-tutorials.ws/voltage-multiplier-circuit.html

Question 101 |

_{i}of 0.25 V and draws 1 mA from the source. If the amplifier delivers 8 V to a load of 10 mA, the power gain is

340 | |

320 | |

250 | |

150 |

Question 102 |

are connected in tandem. The feedback loop is closed through a positive gain of 0.008:

The magnitude of A

_{0}for the system to be oscillatory will be

0.2 | |

0.1 | |

5.0 | |

10.0 |

Question 103 |

_{A}= 10 kΩ, R

_{B}= 50 kΩ, the frequency and the duty cycle will be nearly

1.6 kHz and 54.5% | |

1.3 kHz and 54.5% | |

1.6 KHz and 46.5% | |

1.3 kHz and 46.5% |

Question 104 |

they are guaranteed to be stable and non-linear | |

they are marginally stable and linear. | |

they are guaranteed to be stable and may be constrained to have linear phase | |

they are marginally stable and non-linear |

FIR filters have the following primary advantages:

**They can have exactly linear phase.****They are always stable.****The design methods are generally linear.****They can be realized efficiently in hardware.****The filter startup transients have finite duration.**

Question 105 |

_{BE}from 25

^{0}C to 100

^{0}C for a Silicon Transistor in Fixed Bias Configuration having =100.

(Consider follwing variatio in Silicon transistor parameters with temperature- At T=25

^{0}C, V

_{BE}= 0.65 V and At T = 100

^{0}C. V

_{BE}= 0.5 V)

Change in collector current w.r.t temperature (T)

=

As only is changing with temperature, remaining all are constant.

Therefore, =

= 0.5-0.65

= -0 .15

Given,

After Putting all values in the equation and we get,

Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits

Question 106 |

Current limiting Mode, Constant Current Mode | |

Re-entrant limiting Mode, Current limiting Mode | |

Current limiting Mode, Fold back limiting Mode | |

Fold back limiting Mode, Re-entrant limiting Mode |

**Fold-Back Current Limiting:**When this method is employed if an overload condition exists, the output voltage and current reduce to safe levels. As can be seen from the following curve, should an overload occur the supply will provide current up its current limit point (aka ‘knee’), and then the output current will fold-back to a lower value as the output voltage reduces towards zero.

This technique is employed in linear power supplies because it reduces the strain on the supply’s internal power devices to minimum. One drawback of fold-back current limiting is that if the supply turns on into a heavy capacitive load, it could latch-up at a reduced current before reaching its full output voltage. Depending upon the design, recovery from a fold-back current limit condition can be automatic, or after a built-in time delay when the overload condition is removed.

**Constant Current Limiting :**In this method, should an overload occur, the output current stays at its limit point and the output voltage reduces towards zero in a somewhat linear fashion. This technique is used in many switch mode power supply designs. Typically, the supply will automatically return to its normal output voltage when the overload condition is no longer present.

Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits

Question 107 |

_{0}’ for below circuit whre V

_{in}= Sin (100 t)

2 Sin (100t) | |

Sin (100 t) | |

Sin (200 t) | |

0.5 Sin (100 t) |

from the figure it is clear that it is negative feedback, so voltage at inverting and non-inverting terminal is same .

,

,

and

Apply nodal analysis at ‘A’ & ‘D’

=0

=0

Put , , after solving we get

Sin (100 t)

Refer the Topic Wise Question for Op-Amp and Voltage Reference Circuits Analog Circuits

Question 108 |

_{GS}= V

_{P}/4, where V

_{P}is the Pinch off voltage and drain current, I

_{d}= 0. (Consider (a) Donor Concentration N

_{D}= 10

^{15}electrons/cm

^{3}(b) Channel half-width for V

_{GS}= 0 V is 3).

2.25 | |

3 | |

1.5 | |

0.75 |

Given, ,

For,

As we know, for , →a=b

Here channel width='2'a

Therefore,

=3 →a=3

For any junction , width(depletion) =w=

= ,

]

…………………….(1)

For n-channel,

w=

w=width of junction i.e. (a-b)

………………………………………………………………(2)

On comparing (1) and (2)

For , →b=0 therfore,

Therefore,

Given ,

→b=1.5

Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits

Question 109 |

353.55 V | |

500 V | |

882.3 V | |

1000 V |

W= 400rad/sec

Mutual coupling (M)= K

= 0.5

= 0.5

Transformer equation :

+ 0

250 = (0.2)

…………………………………………………………………………(1)

For secondary,

0.5

Peak value across R 0.5

**=**882.33V

Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits

Question 110 |

Having the following periodical input signal ‘V

_{i}(t)’

(Assume cut-in voltage of the Diode = 0 V; Forward resistance of the Diode = 2 )

1.25 V | |

2.5 V | |

0 V | |

0.1 V |

Multimeter always reads average value of a signal in DC mode.

Graph for

Cut in voltage of diode =0V

Forward resistance () = 2.

For positive half cycle ,D1 is forward biased and it can be replaced by its resistance.

Voltage across 2 is = =

But multimeter is connected in reverse , so voltage in multimeter ()=

= =-0.4V

i.e. waveform for multimeter becomes,

For (-ve half cycle), diode is in off state because it is reversed biased. Therefore circuit becomes

= -

So, complete will be:

Average value =

=

=

= 2.5V

Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits

Question 111 |

^{-1}(0.95) /5 in Radians ln(0.95) -0.051)

4.7 F | |

16.7 p F | |

8.7 p | |

2.7 pF |

The figure shown above is a full wave rectifier with a capacitor filter. We have to find the value of the capacitor C

_{0}.

Now, capacitor C

_{0}= Voltage(Max)/ (2 x freq. x ripple factor x Load resistance)

So, given in question=> Vin=100sin(2ᴨ1000t)

So, now, Voltage(max)=50 volts, Frequency=1000Hz, Ripple factor=2.5 and Load resistance=1000. Putting this value in C

_{0}equation we will get: C

_{0}=1 x 10

^{-5}F

Nearest value will be equal to option (c)

Refer the Topic Wise Question for Simple Diode and Wave Shaping Circuitsa Analog Circuits

Question 112 |

1KHz. | |

1Hz. | |

31.42KHz. | |

31.42MHz. |

Given=> Slew rate= 10ᴨV/ µs, and V

_{out}(peak)=5V

We have to find out the maximum frequency.

So, slew rate is generally given as the rate of change of output voltage with respect to time.

So slew rate= |dV

_{0}/dt|

_{max}

Here, slew rate=10ᴨV/ µs, and V

_{0}(max)=5V

Also, Output Vout= A

_{max *w*}sin2ᴨf

_{max}t

So, Vout is also changing with time.

So, we can write: 10ᴨV/ µs= 5(2ᴨ)f

_{max}(Max Value)

On solving this we get: f

_{max}= 1 Hz

Refer the Topic Wise Question for Op-Amp and Voltage Reference Circuits Analog Circuits

Question 113 |

Thermionic emission of carriers across Schottky barrier | |

Current conduction in Schottky diodes is by majority carriers | |

Switching speed of Schottky diodes is less compared to p-n junction diodes | |

Schottky diode comprises of Metal-Semiconductor junction |

Schottkey diode has a faster switching speed because of negligible reverse recovery time. This results in a little reverse current overshoot as well. Since no re-combination is required due to the use of majority carriers, switching in schottkey diode is much faster than p-n diodes whose switching speed is limited by the recombination time of minority carriers.

Refer the Topic Wise Question for Simple Diode and Wave Shaping Circuitsa Analog Circuits

Question 114 |

_{1}) for Amplifier (A

_{1}) output. If Q

_{1}having low threshold voltage of 0.7 V and negligible ON resistance. 100 p Sec?

What is the duty of output signal of comparator (C

_{1}) after 100 sec?

17.4% | |

34.8 % | |

0% | |

50% |

Here we have to determine the duty of output of Comparator C

_{1}. For determining this, we have to determine V

_{t}.

Now, here a ramp signal is given at V

_{t}. So, for V

_{t}= 5/T

Now, duty cycle= PW/T, where PW=T

_{on}- T=> 'T' being the total time.

So, for finding the duty cycle, we have to find both T

_{on}and T.

Both can be found out by considering gate voltage of N-channel MOSFET.

For the N-channel MOSFET=> Gate voltage V

_{G}can be determined as: V

_{G}= V

_{dc}(1-e

^{-t/т})

Now V

_{t}=0.7volt, and V

_{t}>V

_{G}[V

_{t}is having a ramp signal]

So, we can write: 0.7=5volt(1-)

On solving we will get, t=0.000015sec=15 µsec

So, we have got 't'. Now, we have to determine the output of the first Op-amp. Now,

let the output be V

_{out1}

The only way to determine V

_{out1}is by applying KCL. Before applying, let us take the voltage at the inverting terminal of the first op-amp as V

_{a}and that of non-inverting terminal as V

_{b}

So we can write:

(2.5/3.3) +(2.5-5.5/3) +(2.5 - V

_{out1}/10)=0[By virtual ground property]

On solving this, we will get V

_{out1}= 1.7 Volt.

We have already seen that

V

_{t}= 5/T=> 5 t/T.So, from this we can write: t= V

_{t}x T/5. Now, V

_{t}=V

_{out1}=1.7 volt. So, t= 0.000035seconds=35 µseconds.

So, now T

_{on}= (100+35)=135 µsec, and therefore, we will get duty cycle as: T

_{on}-T/100=35%(given in options)

Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits

Question 115 |

_{B}is?

26.47 A | |

52.94 A | |

13.235 A | |

30.11 A |

Given=> A BJT=> Silicon=> V

_{BE}=0.7V

ß=100, R

_{E}=2.4KΩ, R

_{B}=1.9KΩ, V

_{cc}=10v and V

_{EE}=-8V

We have to determine=> 'I

_{B}' value.

Now, I

_{B}= I

_{c}/ß

Applying KVL in base emitter side:

V

_{BE}+I

_{E}R

_{E}+V

_{EE}=0=> I

_{E}= (-V

_{EE}-V

_{BE})/R

_{E}

On putting the values given in question, we get: I

_{E}= 3.041mA

Now, I

_{B}= I

_{E}/(1+ß)=> 30.11 µA

Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits