Analog Circuits Subject WIse
Question 1 |
In the circuit shown, Vs is a square wave of period T with maximum and minimum values of 8 V and -10 V, respectively. Assume that the diode is ideal and R1 = R2 = 50 Ω.
The average value of VL is _________ volts (rounded off to 1 decimal place).
The average value of VL is _________ volts (rounded off to 1 decimal place).
Fill in the Blank Type Question |
Question 1 Explanation:
Question 2 |
In the circuit shown, the threshold voltages of the pMOS (|Vtp|) and nMOS (Vtn) transistors are both equal to 1 V. All the transistors have the same output resistance rds of 6 MΩ. The other parameters are listed below.
Μn and μp are the carrier mobilites, and Cox is the oxide capacitance per unit area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is ____________(rounded off to 1 decimal place).
Fill in the Blank Type Question |
Question 2 Explanation:
Question 3 |
Consider a long-channel MOSFET with a channel length 1 μm and width 10 μm. The device parameters are
acceptor concentration NA = 5 × 1016 cm-3,
electron mobility μn = 800 cm2/V-s,
oxide capacitance/area Cox = 3.45 × 10-7 F/cm2,
threshold voltage VT = 0.7 V.
The drain saturation current (IDsat) for a gate voltage of 5 V is ____________ mA (rouonded off to two decimal places).
acceptor concentration NA = 5 × 1016 cm-3,
electron mobility μn = 800 cm2/V-s,
oxide capacitance/area Cox = 3.45 × 10-7 F/cm2,
threshold voltage VT = 0.7 V.
The drain saturation current (IDsat) for a gate voltage of 5 V is ____________ mA (rouonded off to two decimal places).
[ε0 = 8.854 × 10-14 F/cm, εsi = 11.9]
Fill in the Blank Type Question |
Question 3 Explanation:
Question 4 |
In the circuit shown, V1 = 0 and V2 = Vdd. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of Iout is ___________ mA (rounded off to 1 decimal place).
Fill in the Blank Type Question |
Question 4 Explanation:
Question 5 |
A CMOS inverter, designed to have a mid-point voltage VI equal to half of Vdd, as shown in the figure, has the following parameters :
Vdd = 3 V
μnCox = 100 μA/V2 ; Vtn = 0.7 V for nMOS
μnCox = 40 μA/V2 ; |Vtp| = 0.9 V for pMOS
The ratio of 
to 
is equal to __________ (rounded off to 3 decimal places).
Fill in the Blank Type Question |
Question 5 Explanation:
Question 6 |
In the circuit shown, Vs is a 10 V square wave of period, T = 4 ms with R = 500 Ω and C = 10 μF. The capacitor is initially uncharged at t = 0, and the diode is assumed to be ideal. The voltage across the capacitor (Vc) at 3 ms is equal to ________ volts (rounded off to one decimal place).
Fill in the Blank Type Question |
Question 6 Explanation:
Question 7 |
In the circuit shown, the breakdown voltage and the maximum current of the Zener diode are 20 V and 60 mA, respectively. The values of R1 and RL are 200 Ω and 1 kΩ, respectively. What is the range of Vi that will maintain the Zener diode in the ‘on’ state?
18 V to 24 V | |
20 V to 28 V | |
24 V to 36 V | |
22 V to 34 V |
Question 7 Explanation:
Question 8 |
For the operational amplifier circuit shown, the output saturation voltages are ±15V. The upper and lower threshold voltages for the circuit are, respectively.
+5V and -5V | |
+7V and -3V | |
+3V and -7V | |
+3V and -3V |
Question 8 Explanation:
Question 9 |
A good transconductance amplifier should have
High input impedance and low output impedance | |
Low input impedance and high output impedance | |
High input and output impedances | |
Low input and output impedances |
Question 9 Explanation:
->A good transconductance amplifier has current as output and voltage as input that means it should have high input and high output impedances.
->A good trans conductance amplifier should have high input and output resistance
->A good trans conductance amplifier should have high input and output resistance
Question 10 |
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain,
and an open-loop cut-off frequency, fc= 8 Hz. The voltage gain of the amplifier at 15kHz, in V/V, is ______. 
Fill in the Blank Type Question |
Question 10 Explanation:
Question 11 |
A good transimpedance amplifier has
low input impedance and high output impedance | |
high input impedance and high output impedance | |
high input impedance and low output impedance | |
low input impedance and low output impedance |
Question 11 Explanation:
A good transimpedance amplifier should have low input impedance and low output impedance
Question 12 |
In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5 volts. At the input, unit step voltage is applied i.e. 
Also at 
the voltage across each of the capacitors is zero
The time in milliseconds, at which the output voltage crosses – 10 V is
Also at the voltage across each of the capacitors is zero
The time in milliseconds, at which the output voltage crosses – 10 V is
2.5 | |
5 | |
7.5 | |
10 |
Question 12 Explanation:
Question 13 |
A DC current of 26 μA flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, the diode has a junction capacitance of 0.5 nF. Its neutral region resistances can be neglected. Assume that the room temperature thermal equivalent voltage is 26 mV.
For
the amplitude of the small-signal component of diode current (in μA, correct to one decimal place) is ___________.
For
the amplitude of the small-signal component of diode current (in μA, correct to one decimal place) is ___________.
Fill in the Blank Type Question |
Question 13 Explanation:
Question 14 |
An op-amp based circuit is implemented as shown below.
In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place) at node A, connected to the negative input of the op-amp as indicated in the figure is ___________.
Fill in the Blank Type Question |
Question 14 Explanation:
Question 15 |
The circuit shown in the figure is used to provide regulated (5 V) across the 1 
resistor. Assume that the Zener diode has a constant reverse breakdown voltage for a current range, starting from a minimum required Zener current, 
to its maximum allowable current. The input voltage 
may vary by 5% from its nomial value of 6 V. The resistance of the diode in the breakdown region is negligible.
The value of R and the minimum required power dissipation rating of the diode, respectively, are
resistor. Assume that the Zener diode has a constant reverse breakdown voltage for a current range, starting from a minimum required Zener current, to its maximum allowable current. The input voltage may vary by 5% from its nomial value of 6 V. The resistance of the diode in the breakdown region is negligible. The value of R and the minimum required power dissipation rating of the diode, respectively, are
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Question 15 Explanation:
Question 16 |
An n-channel enhancement mode MOSFET is biased at VGS>VTH and, VDS>(VGS-VTH), where VGSis the gate-to-source voltage, VDS is the drain-to-source voltage and VTH is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves like a
Voltage source with zero output impedance | |
Voltage source with non-zero output impedance | |
Current source with finite output impedance | |
Current source with infinite output impedance |
Question 16 Explanation:
The small signal equivalent circuit of MOSFET in saturation is as shown in below figure
It indicates that MOSFET is working in saturation region
and it can be used as an amplifier.
So it can act as current source with finite output impedance.
Hence Option(c) is correct
It indicates that MOSFET is working in saturation regionand it can be used as an amplifier.
So it can act as current source with finite output impedance.
Hence Option(c) is correct
Question 17 |
In the figure, D1 is a real silicon pn junction diode with a drop of 0.7V under forward bias condition and D2 is a zener diode with breakdown voltage of -6.8 V. The input Vin(t) is a periodic square wave of period T, whose one period is shown in the figure.
Assuming 10 τ <<T. where τ is the time constant of the circuit, the maximum and minimum values of the output waveform are respectively.
Assuming 10 τ <<T. where τ is the time constant of the circuit, the maximum and minimum values of the output waveform are respectively.
7.5 V and –20.5V | |
6.1 V and –21.9V | |
7.5 V and –21.2 V | |
6.1 V and –22.6 V |
Question 17 Explanation:
Question 18 |
Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double that of T1. Both the transistors are biased in the saturation region of operation, but the gate overdrive voltage (VGS-VTH) of T2 is double that of T1, where VGS and VTH are the gate – to – source voltage and threshold voltage of the transistors, respectively. If the drain current and transconductance of T1 are ID1 and gm1 respectively, the corresponding values of these two parameters for T2 are
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Question 18 Explanation:
Question 19 |
In the circuit shown, transistors Q1 and Q2 are biased at a collector current of 2.6mA. If transistor current gains are sufficiently large to assume collector current equal to emitter current and thermal voltage of 26 mV, the magnitude of voltage gain V0/Vs in the mid-band frequency range is __________ (up to second decimal place).
Fill in the Blank Type Question |
Question 19 Explanation:
A.C equivalent circuit for the given figure
Question 20 |
Consider the constant current source shown in the figure below. Let p represent the current gain of the transistor.
The load current Io through RL is
The load current Io through RL is  | |
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Question 20 Explanation:
Voltage at (+) terminal 
Voltage at emitter of PNP BJT
The current
through R
Voltage at emitter of PNP BJT
The current
through R Question 21 |
The following signal V; of peak voltage 8V is applied to the non-inverting terminal of an ideal op-amp. The transistor has
The number of times the LED glows is
The number of times the LED glows isFill in the Blank Type Question |
Question 21 Explanation:
LED will glow when Vi > 2 V
Here Vi crosses 2 V, 3 times
Therefore LED glows 3 times
Correct Answer is 3
Question 22 |
Consider the oscillator circuit shown in the figure. The function of the network (shown in dotted lines) consisting of the 
resistor in series with the two diodes connected back-to-back is to:
resistor in series with the two diodes connected back-to-back is to:
Introduce amplitude stabilization by preventing the op amp from saturating and thus producing sinusoidal oscillations of fixed amplitude | |
Introduce amplitude stabilization by forcing the op-amp to swing between positive and negative saturation and thus producing square wave oscillations of fixed amplitude | |
Introduce frequency stabilization by forcing the circuit to oscillate at a single frequency | |
Enable the loop gain to take on a value that produces square wave oscillations |
Question 22 Explanation:
The circuit shown is a wein bridge oscillator. The amplitude
of oscillations can be determined and stabilized by using
a nonlinear control network. As the oscillations grow, the
diodes start to conduct causing the effective resistance
in the feedback to decrease. Equilibrium will be reached
at the output amplitude that causes the loop gain to be
exactly unity.
Question 23 |
The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-N counter (comprising ÷2, ÷4, ÷8, ÷16 outputs) is sketched below. The synthesizer is excited with a 5 kHz signal (Input 1). The free-running frequency of the PLL is set to20 kHz. Assume that the commutator switch makes contacts repeatedly in the order 1-2-3-4.
The corresponding frequencies synthesized are:
The corresponding frequencies synthesized are:
10 kHz, 20 kHz, 40 kHz, 80 kHz | |
20 kHz, 40 kHz, 80 kHz, 160 kHz | |
80 kHz, 40 kHz, 20 kHz, 10 kHz | |
160 kHz, 80 kHz, 40 kHz, 20 kHz |
Question 23 Explanation:
Question 24 |
What is the voltage V0 in the following circuit?
OV | |
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Switching threshold of inverter | |
VDD |
Question 24 Explanation:
The transfer characteristics of the CMOS inverter is as follows
Since the inverter is connected in feedback loop formed by connecting 1OXQ resistor between the output and input, the output goes and stays at the middle of the characteristics
Switching threshold of inverter
Since the inverter is connected in feedback loop formed by connecting 1OXQ resistor between the output and input, the output goes and stays at the middle of the characteristics
Switching threshold of inverterQuestion 25 |
An ideal op-amp has voltage sources V1, V3, V5, ..., VN-1 connected to the non-inverting input and V2,V4, V6, ..., VN connected to the inverting input as shown in the figure below (+Vcc= 15 volt,—Vcc= —15 volt). The voltages V1, V2, V3, V4, V5, V6,... are 1, — 1/2, 1/3, —1/4, 1/5, —1/6,... volt, respectively. As N approaches infinity, the output voltage (in volt) is
Fill in the Blank Type Question |
Question 25 Explanation:
Question 26 |
For the circuit with ideal diodes shown in the figure, the shape of the output (υout) for the given sine wave input (υin) will be
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Question 26 Explanation:
Diode circuit can be simplified as shown below
During positive pulse, both diodes are forward biased.
During negative pulse, both diodes are reverse biased.
So, Vo = 0V
Hence, the correct option is (C).
During positive pulse, both diodes are forward biased.
During negative pulse, both diodes are reverse biased.
So, Vo = 0V
Hence, the correct option is (C).
Question 27 |
A MOSFET in saturation has a drain current of 1 mA for VDS = 0.5 V. If the channel length modulation coefficient is 0.05 V–1, the output resistance (in kΩ) of the MOSFET is _______.
Fill in the Blank Type Question |
Question 27 Explanation:
Under channel length modulation
Question 28 |
For the NMOSFET in the circuit shown, the threshold voltage is Vth, where Vth > 0. The source voltage VSS is varied from 0 to VDD. Neglecting the channel length modulation, the drain current ID as a function of VSS is represented by
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Question 28 Explanation:
Hence MOS transistor is in saturation.
In saturation,
As Vss increases ID decreases (Not linearly because square factor)
Hence option A. is correct.
Question 29 |
The circuit shown in the figure has an ideal opamp. The oscillation frequency and the condition to sustain the oscillations, respectively, are
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Question 29 Explanation:
Question 30 |
Assume that the diode in the figure has 
, but is otherwise ideal.
The magnitude of the current i2 (in mA) is equal to _____.
, but is otherwise ideal.
The magnitude of the current i2 (in mA) is equal to _____.
Fill in the Blank Type Question |
Question 30 Explanation:
Let the Diode is in the OFF state.
net current I=2/(6+2)=0.25mA
so voltage drop across diode=0.25*2=0.5V
our assumption of diode is off is correct
so current will be
I2 = 2/8k = 0.25mA
net current I=2/(6+2)=0.25mA
so voltage drop across diode=0.25*2=0.5V
our assumption of diode is off is correct
so current will be
I2 = 2/8k = 0.25mA
Question 31 |
Resistor R1 in the circuit below figure has been adjusted so that I1 = 1 mA. The bipolar transistors Q1 and Q2 are perfectly matched and have very high current gain, so their base currents are negligible. The supply voltage Vcc is 6 V. The thermal voltage kT/q is
26 mV.
The value of R2 (in ohms) for which I2 =100μA is...........
26 mV.
The value of R2 (in ohms) for which I2 =100μA is...........
Fill in the Blank Type Question |
Question 31 Explanation:
From above circuits,
,.....................(i)
,........................(ii)
from equation (i) & (ii),
,.....................(i),........................(ii)from equation (i) & (ii),
Question 32 |
Which one of the following statements is correct about an ac-coupled common-emitter amplifier operating in the mid-band region?
The device parasitic capacitances behave like open circuits, whereas coupling and by pass capacitances behave like short circuits. | |
The device parasitic capacitances, coupling capacitances and bypass capacitances behave like open circuits. | |
The device parasitic capacitances, coupling capacitances and bypass capacitances behave like short circuits. | |
The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances behave like open circuits. |
Question 32 Explanation:
The parasitic capacitances are in PF and the coupling and bypass capacitors are in μF. Therefore, for the mid frequency band, parasitic capacitance act like open circuits and coupling and bypass capacitances act like short circuits.
Question 33 |
The figure shows a half-wave rectifier with a 
filter capacitor. The load draws a constant current Io= 1 A from the rectifier. The figure also shows the input voltage Vi, the output voltage Vc and the peak-to-peak voltage ripple u on Vc. The input voltage V1 is a triangle-wave with an amplitude of 10 V and a period of 1ms
The value of the ripple u (in volts) is ____
filter capacitor. The load draws a constant current Io= 1 A from the rectifier. The figure also shows the input voltage Vi, the output voltage Vc and the peak-to-peak voltage ripple u on Vc. The input voltage V1 is a triangle-wave with an amplitude of 10 V and a period of 1ms
The value of the ripple u (in volts) is ____
Fill in the Blank Type Question |
Question 33 Explanation:
Peak to peak ripple voltage
Vripple = 2.1 Volts
Vripple = 2.1 Volts
Question 34 |
In the op-amp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage Vo to +5 V or -5V. The switch S is initially closed and is opened at time t=0
The time t = t1 (in seconds) at which Vo changes state is ____
The time t = t1 (in seconds) at which Vo changes state is ____
Fill in the Blank Type Question |
Question 34 Explanation:
Question 35 |
An op-amp has a finite open loop voltage gain of 100. Its input offset voltage
Vios(= +5 mV)
is modeled as shown in the circuit below. The amplifier is ideal in all other respects.
Vinput Is 25 mV
The output voltage (in millivolts) is _____
Vinput Is 25 mV
The output voltage (in millivolts) is _____
Fill in the Blank Type Question |
Question 35 Explanation:
The gain of the practical op-amp
Question 36 |
Consider the circuit shown in the figure. Assuming 
volt, the value of the dc voltage 
(in volts) is _______.
volt, the value of the dc voltage (in volts) is _______.
Fill in the Blank Type Question |
Question 36 Explanation:
Question 37 |
In the Astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin 3 is ___________
Fill in the Blank Type Question |
Question 37 Explanation:
Question 38 |
For the circuit shown in the figure,
and 
If the input 
then the overall voltage gain 
of the circuit is ______.
and If the input then the overall voltage gain of the circuit is ______.
Fill in the Blank Type Question |
Question 38 Explanation:
The overall voltage gain
Question 39 |
In the circuit shown in the figure, the channel length modulation of all transistors is non-zero 
Also, all transistors operate in saturation and have negligible body effect. The ac small signal voltage gains 
of the circuit is
Also, all transistors operate in saturation and have negligible body effect. The ac small signal voltage gains of the circuit is
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Question 39 Explanation:
Question 40 |
In the circuit shown in the figure, transistor M1 is in saturation and has transconductance
gm = 0.01 siemens. Ignoring internal parasitic capacitances and assuming the channel length modulation
to be zero, the small signal input pole frequency (in kHz) is.
gm = 0.01 siemens. Ignoring internal parasitic capacitances and assuming the channel length modulation
to be zero, the small signal input pole frequency (in kHz) is.
Fill in the Blank Type Question |
Question 40 Explanation:
Question 41 |
In the circuit shown, the voltage Vx (in Volts) is______
Fill in the Blank Type Question |
Question 41 Explanation:
Question 42 |
An npn BJT having reverse saturation current Is = 10–15 A is biased in the forward active region with VBE = 700 mV. The thermal voltage (VT) is 25 mV and the current gain (b) may vary from 50 to 150 due to manufacturing variations. The maximum emitter current (in mA) is___.
Fill in the Blank Type Question |
Question 42 Explanation:
Question 43 |
In the circuit shown, assume that the opamp is ideal. If the gain (v0 / vin) is –12, the value of R (in kΩ) is _____.
Fill in the Blank Type Question |
Question 43 Explanation:
Given
Question 44 |
In the circuit shown, assume that the diodes D1 and D2 are ideal. The average value of voltage Vab (in volts), across terminals ‘a’ and ‘b’ is ________.
Fill in the Blank Type Question |
Question 44 Explanation:
Question 45 |
If the circuit shown has to function as a clamping circuit, which one of the following conditions should be satisfied for sinusoidal signal of period T?
RC << T | |
RC = 0.35T | |
RC  T | |
RC >> T |
Question 45 Explanation:
->Time constant = t = RC
If RC >> T = period of sinusoid
Then the capacitor will not play its role i.e. it will not discharge and clamping will take place.
->For an ideal clamping circuit once the capacitor is charged it should not discharge. Hence discharging time constant (RC) must be much larger than the time period of input signal. i.e. RC >> T
If RC >> T = period of sinusoid
Then the capacitor will not play its role i.e. it will not discharge and clamping will take place.
->For an ideal clamping circuit once the capacitor is charged it should not discharge. Hence discharging time constant (RC) must be much larger than the time period of input signal. i.e. RC >> T
Question 46 |
In the circuit shown, V0 = V0A for switch SW in position A and V0 = V0B for SW in position B. Assume that the opamp is ideal. The value of 
is _____________
is _____________
1.5 | |
4 | |
10 | |
15 |
Question 46 Explanation:
Hence VOB / VOA = -6/-5= 6/5 =1.5
Question 47 |
In the ac equivalent circuit shown, the two BJTs are biased in active region and have identical parameters with β >> 1. The open circuit small signal voltage gain is approximately___________
1 | |
-1 | |
0 | |
2 |
Question 47 Explanation:
Question 48 |
The diode in the circuit given below has VON = 0.7 V but is ideal otherwise. The current (in mA) in the 4kΩ resistor is______ mA
0.6 | |
1.6 | |
1.5 | |
4 |
Question 48 Explanation:
Question 49 |
If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET, it will lead to
a decrease in the threshold voltage | |
channel length modulation | |
an increase in substrate leakage current | |
an increase in accumulation capacitance |
Question 49 Explanation:
If fixed positive charges are present in oxide, then
VTH = VFB - Qox/Cox
Therefore, threshold voltage decreases.
VTH = VFB - Qox/Cox
Therefore, threshold voltage decreases.
Question 50 |
A good current buffer has
Low input impedance and low output impedance | |
Low input impedance and high output impedance | |
High input impedance and low output impedance | |
High input impedance and high output impedance |
Question 50 Explanation:
So, a good currrent buffer should have low input impedance and high output impedance.
Question 51 |
In the ac equivalent circuit shown in the figure, if iin is the input current and RF is very large, the type of feedback is
voltage-voltage feedback | |
voltage-current feedback | |
current-voltage feedback | |
current-current feedback |
Question 51 Explanation:
Output sample is voltage and is added to the input current.
Since, feedback is diectly connected to output so the sampling is voltage and mixing is current type.
∴ It is voltage – shunt negative feedback i.e., voltage-current negative feedback
Since, feedback is diectly connected to output so the sampling is voltage and mixing is current type.
∴ It is voltage – shunt negative feedback i.e., voltage-current negative feedback
Question 52 |
In the low-pass filter shown in the figure, for a cut-off frequency of 5kHz, the value of R2(in 
) is ____________.
) is ____________. 2.24 | |
2.82 | |
3.18 | |
3.42 |
Question 52 Explanation:
Given f = 5KHz
Question 53 |
In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R are,
4 V, 3 V, 2 V | |
5 V, 5 V, 5 V | |
4 V, 4 V, 4 V | |
5 V, 4 V, 3 V |
Question 53 Explanation:
Assume NMOS are in saturation
Question 54 |
A BJT is biased in forward active mode, Assume 
and reverse saturation current 
The trans conductance of the BJT (in mA/V) is ________.
and reverse saturation current The trans conductance of the BJT (in mA/V) is ________.
4.425 | |
4.475 | |
5.525 | |
5.785 |
Question 54 Explanation:
Question 55 |
In the voltage regulator circuit shown in the figure, the op-amp is ideal. The BJT has
VBE = 0.7V and β = 100, and the zener voltage is 4.7V. For a regulated output of 9 V, the value of R(inW) is ______ .
VBE = 0.7V and β = 100, and the zener voltage is 4.7V. For a regulated output of 9 V, the value of R(inW) is ______ .
893 | |
993 | |
1093 | |
1193 |
Question 55 Explanation:
Question 56 |
In the circuit shown, the op-amp has finite input impedance, infinite voltage gain and zero input offset voltage. The output voltage Vout is
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Question 56 Explanation:
Given, Zi = finite
A = ∞
V2 = (R1||R2)I1
=
KCL at inverting node
A = ∞
V2 = (R1||R2)I1
=
KCL at inverting node
Question 57 |
For the amplifier shown in the figure, the BJT parameters are
VBE = 0.7V and β = 200,
and thermal voltage VT = 25mV
The voltage gain ( Vo / Vi )
of the amplifier is _______
137.76 | |
-137.76 | |
237.76 | |
-237.76  |
Question 57 Explanation:
Question 58 |
An increase in the base recombination of a BJT will
The common emitter dc current gain  decreases | |
the breakdown voltage  | |
the unity-gain cut-off frequency fT | |
the trans conductance gm |
Question 58 Explanation:
As recombination current increases the collector current reduces hence the β reduces
Question 59 |
In CMOS technology, shallow P-well or N-well regions can be formed using
low pressure chemical vapour deposition | |
low energy sputtering | |
low temperature dry oxidation | |
low energy ion-implantation |
Question 59 Explanation:
- In CMOS, an n-well is used to fabricate PMOS if the substrate is p-type.
- In CMOS, p-well is used to fabricate NMOS if the substrate is n-type.
- For n-well CMOS process, an initial thick oxide layer (5000 Ao ) is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms usually phosphorous are implanted through this window in the oxide.
Question 60 |
The feedback topology in the amplifier circuit (the base bias circuit is not shown for simplicity) in the figure is
Voltage shunt feedback | |
Current series feedback | |
Current shunt feedback | |
Voltage series feedback |
Question 60 Explanation:
By opening the output feedback signed becomes zero. Hence it is current sampling. As the feedback signal vf is subtracted from the signal same vs it is series mixing.
Question 61 |
In the differential amplifier shown in the figure, the magnitudes of the common-mode and differential-mode gains are Acm and Ad, respectively. If the resistance RE is increased, then
Acm increases | |
Common-mode rejection ratio increases | |
Ad increases | |
Common-mode rejection ratio decreases |
Question 61 Explanation:
Ad does not depend on RE
Acm decreases as RE is increased
CMRR for differential amplifier is given by,
As Acm decreases CMRR increases
Acm decreases as RE is increased
CMRR for differential amplifier is given by,
As Acm decreases CMRR increases
Question 62 |
A cascade connection of two voltage amplifiers A1 and A2 is shown in the figure. The open-loop gain Av0, input resistance Rin, and output resistance RO for A1 and A2 are as follows:
The approximate overall voltage gain Vout /Vin is __________.
The approximate overall voltage gain Vout /Vin is __________.
28.50 | |
32.0 | |
33.0 | |
34.722 |
Question 62 Explanation:
Question 63 |
For the n-channel MOS transistor shown in the figure, the threshold voltage VTh is 0.8 V. Neglect channel length modulation effects. When the drain voltage VD = 1.6 V, the drain current ID was found to be 0.5 mA. If VD is adjusted to be 2 V by changing the values of R and VDD, the new value of ID (in mA) is
0.625 | |
0.75 | |
1.125 | |
1.5 |
Question 63 Explanation:
Question 64 |
For the MOSFETs shown in the figure, the threshold voltage
The value of ID (in mA) is ________.
The value of ID (in mA) is ________.
0.6 mA | |
0.7 mA | |
0.8 mA | |
0.9 mA |
Question 64 Explanation:
Question 65 |
In MOSFET fabrication, the channel length is defined during the process of
Isolation oxide growth | |
Channel stop implantation | |
Poly-silicon gate patterning | |
Lithography step leading to the contact pads |
Question 65 Explanation:
Though MOSFET stands for metal oxide semiconductor FET, but practically a polycrystalline Si (or
poly Si) is deposited above the gate. The channel length is defined during the process of poly-silicon
gate patterning.
Question 66 |
The desirable characteristics of a transconductance amplifier are
High input resistance and high output resistance | |
High input resistance and low output resistance | |
Low input resistance and high output resistance | |
Low input resistance and low output resistance |
Question 66 Explanation:
Transconductance amplifier must have zi = ∞ and zo= ∞
Question 67 |
In the circuit shown, the PNP transistor has 
Assume that 
. For
Vo to be 5V ,
the value of 
___________
Assume that . For
Vo to be 5V ,
the value of ___________
1.075 | |
1.175 | |
2.075 | |
2.175 |
Question 67 Explanation:
Question 68 |
The figure shows a half-wave rectifier. The diode D is ideal. The average steady-state current (in Amperes) through the diode is approximately ____________.
0.07 | |
0.08 | |
0.09 | |
1.0 |
Question 68 Explanation:
Question 69 |
Let 
be sampled at 20 Hz and reconstructed using an ideal low-pass filter with cut-off frequency of 20 Hz. The frequency/frequencies present in the reconstructed signal is/are
be sampled at 20 Hz and reconstructed using an ideal low-pass filter with cut-off frequency of 20 Hz. The frequency/frequencies present in the reconstructed signal is/are 5 Hz and 15 Hz only | |
10 Hz and 15 Hz only | |
5 Hz, 10 Hz and 15 Hz only | |
5 Hz only |
Question 69 Explanation:
Spectrum of x(t)
Spectrum of sampled version of x(t)
After LPF, signal will contain 5 and 15Hz component only
Question 70 |
For an all-pass system
for all
ω
If Re(a) ≠ O, lm(a) ≠ O then b equals
for all
ω
If Re(a) ≠ O, lm(a) ≠ O then b equals
a | |
a* | |
1/a* | |
1/a |
Question 70 Explanation:
Question 71 |
The slope of the 
curve of an n-channel MOSFET in linear regime is
at 
For the same device, neglecting channel length modulation, the slope of the
under saturation regime is approximately ___________.
curve of an n-channel MOSFET in linear regime is at For the same device, neglecting channel length modulation, the slope of the
under saturation regime is approximately ___________.
0.05 | |
0.06 | |
0.07 | |
0.08 |
Question 71 Explanation:
Question 72 |
An ideal MOS capacitor has boron doping-concentration of 1015 cm-3 in the substrate. When a gate voltage is applied, a depletion region of width 
is formed with a surface (channel) potential of 0.2 V. Given that 
and the relative permittivities of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/μm) in the oxide region is __________________.
is formed with a surface (channel) potential of 0.2 V. Given that and the relative permittivities of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/μm) in the oxide region is __________________.
1.6 | |
2.0 | |
2.4 | |
2.8 |
Question 72 Explanation:
Question 73 |
In the circuit shown, the silicon BJT has
β=50
Assume
VBE =0.7 V and VCE(sat) =0.2 V
Which one of the following statements is correct?
For RC = 1  the BJT operates in the saturation region | |
For RC = 3  , the BJT operates in the saturation region | |
For RC =20  , the BJT operates in the cut-off region | |
For RC =20  , the BJT operates in the linear region |
Question 73 Explanation:
Question 74 |
Assuming that the Op-amp in the circuit shown is ideal, VO is given by
 | |
 | |
 | |
 |
Question 74 Explanation:
The Correct Answer Among All the Options is D
Virtual ground and KCL at inverting terminal gives
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Virtual ground and KCL at inverting terminal gives
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Question 75 |
For the MOSFET M1 shown in the figure, assume W/L = 2,
The transistor M1 switches from saturation region to linear region when Vin (in Volts) is _______
The transistor M1 switches from saturation region to linear region when Vin (in Volts) is _______
1.0 | |
1.5 | |
2.0 | |
2.5 |
Question 75 Explanation:
Question 76 |
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
 | |
 | |
 | |
 |
Question 76 Explanation:
For an SRAM construction 4 MOSFETs are required (2-PMOS and 2-NMOS) with interchanged outputs connected to each CMOS inverter. This condition is followed in option (B)
Question 77 |
If the emitter resistance in a common-emitter voltage amplifier is not bypassed, it will
Reduce both the voltage gain and the input impedance | |
Reduce the voltage gain and increase the input impedance | |
Increase the voltage gain and reduce the input impedance | |
Increase both the voltage gain and the input impedance |
Question 77 Explanation:
When a Common-Emitter amplifier’s emitter resistance is not by passed, due to the negative feedback the voltage gain decreases and input impedance increases
Question 78 |
Two silicon diodes, with a forward voltage drop of 0.7 V, are used in the circuit shown in the figure. The range of input voltage Vi
for which the output voltage Vo = Vi is
 | |
 | |
 | |
 |
Question 78 Explanation:
Question 79 |
The circuit shown represents:
A bandpass filter | |
A voltage controlled oscillator | |
An amplitude modulator | |
A monostable multivibrator |
Question 79 Explanation:
A monostable multivibrator
A monostable multivibrator, also called a one shot, is a sequential logic electronic circuit that generates an output pulse. When triggered, a pulse of pre-defined duration is produced. The circuit then returns to its stable state and produces no more output until triggered again.
A monostable multivibrator, also called a one shot, is a sequential logic electronic circuit that generates an output pulse. When triggered, a pulse of pre-defined duration is produced. The circuit then returns to its stable state and produces no more output until triggered again.
Question 80 |
Consider two BJTs biased at the same collector current with area
Assuming that all other device parameters are identical, kT/q = 26 mV, the intrinsic carrier concentration is
the difference
between the base-emitter voltages (in mV) of the two BJTs
361 | |
381 | |
412 | |
418 |
Question 80 Explanation:
Question 81 |
Consider the common-collector amplifier in the figure (bias circuitry ensures that the transistor operates in forward active region, but has been omitted for simplicity). Let 
be the collector current, 
be the base-emitter voltage and 
be the thermal voltage. Also, 
and 
are the small-signal trans conductance and output resistance of the transistor, respectively. Which one of the following conditions ensures a nearly constant small signal voltage gain for a wide range of values of
?
be the collector current, be the base-emitter voltage and be the thermal voltage. Also, and are the small-signal trans conductance and output resistance of the transistor, respectively. Which one of the following conditions ensures a nearly constant small signal voltage gain for a wide range of values of?
 | |
 | |
 | |
 |
Question 81 Explanation:
Question 82 |
A BJT in a common-base configuration is used to amplify a signal received by a 50
antenna. Assume kT/q = 25 mV. The value of the collector bias current (in mA) required to match the input impedance of the amplifier to the impedance of the antenna is________.
antenna. Assume kT/q = 25 mV. The value of the collector bias current (in mA) required to match the input impedance of the amplifier to the impedance of the antenna is________. 0.2 | |
0.4 | |
0.5 | |
0.75 |
Question 82 Explanation:
Input impedance of Common Base amplifier,
zi = re = VI / IE
zi = re = VI / IE
Question 83 |
For the common collector amplifier shown in the figure, the BJT has high
β
, negligible
VCE(sat) and VBE = 0.7V
The maximum undistorted peak-to-peak output voltage
Vo
(in Volts)is______.
9.6 | |
8.3 | |
8.9 | |
9.4 |
Question 83 Explanation:
Question 84 |
In the circuit shown below what is the output voltage (Vout) if a silicon transistor Q and an ideal op-amp are used?
15 V | |
–0.7 V | |
+0.7 V | |
+15 V |
Question 84 Explanation:
For the given ideal op-amp, negative terminal will be also ground (at zero voltage) and so, the collector terminal of the BJT will be at zero voltage.
i.e.,
The current in
resistor is given by
This current will flow completely through the BJT since, no current will flow into the ideal op-amp (I/P resistance of ideal op-amp is infinity). So, for BJT we have
i.e., the base collector junction is reverse biased (zero voltage) therefore, the collector current (IC) can have a value only if base-emitter is forward biased.
Hence,
i.e.,
The current in
resistor is given by This current will flow completely through the BJT since, no current will flow into the ideal op-amp (I/P resistance of ideal op-amp is infinity). So, for BJT we have
i.e., the base collector junction is reverse biased (zero voltage) therefore, the collector current (IC) can have a value only if base-emitter is forward biased.
Hence,
Question 85 |
In a voltage-voltage feedback as shown below, which one of the following statements is TRUE if the gain k is increased?
The input impedance increases and output impedance decreases. | |
The input impedance increases and output impedance also increases. | |
The input impedance decreases and output impedance also decreases. | |
The input impedance decreases and output impedance increases. |
Question 85 Explanation:
Given i/p voltage
If k increased then input voltage is also increased so, the input impedance increases.
Now, we have
Since, Vin is independent of k when seen from output mode, the output voltage decreases with increase in k that leads to the decrease of output impedance. Thus, input impedance increases and output impedance decreases.
If k increased then input voltage is also increased so, the input impedance increases.
Now, we have
Since, Vin is independent of k when seen from output mode, the output voltage decreases with increase in k that leads to the decrease of output impedance. Thus, input impedance increases and output impedance decreases.
Question 86 |
In a MOSFET operating in the saturation region, the channel length modulation effect causes
an increase in the gate-source capacitance | |
a decrease in the transconductance | |
a decrease in the unity-gain cutoff frequency | |
a decrease in the output resistance |
Question 86 Explanation:
In a MOSFET operating in the saturation region, the channel length modulation effect causes a decrease in output resistance.
Without the channel length modulation the drain current of a MOSFET is given by,
Id = μ/2 x C(W/L)(Vgs - Vt)²
∴ dI/dV = 0
=> dV/dI = ∞
=> Rd = ∞
If we consider channel length modulation, the value of Rd will be always less than ∞ .
So, channel length modulation decreases the output resistance.
Without the channel length modulation the drain current of a MOSFET is given by,
Id = μ/2 x C(W/L)(Vgs - Vt)²
∴ dI/dV = 0
=> dV/dI = ∞
=> Rd = ∞
If we consider channel length modulation, the value of Rd will be always less than ∞ .
So, channel length modulation decreases the output resistance.
Question 87 |
In the circuit shown below, the knee current of the ideal Zener diode is 10 mA. To maintain 5 V across RL, the minimum value of RL in Q and the minimum power rating of the Zener diode in mW, respectively, are
125 and 125 | |
125 and 250 | |
250 and 125 | |
250 and 250 |
Question 87 Explanation:
Question 88 |
The small signal resistance (i.e., dVB/dID) in kΩ offered by the n-channel MOSFET M shown in the figure below, at a bias point of VB = 2 V is (devise data for M: device transconductance parameter 
, threshold voltage 
, and neglect body effect and channel length modulation effects)
, threshold voltage , and neglect body effect and channel length modulation effects) 12.5 | |
25 | |
50 | |
100 |
Question 88 Explanation:
Given,
So, we have
Drain voltage
Therefore,
and
So, the MOSFET is in the saturation region. Therefore, drain current is
ID = 1/2 Kn(VGS - VT)2 (Rest part i.e. 1 + λVDS is neglected as mentioned in question)
2ID = Kn (VB-1)2
Differentiating both side with respect to ID
2 = Kn 2(VB-1)(dVB/dID)
Since,
(at D.C. Voltage)
Hence, to get small signal resistance
dVB/dID = 2/Kn 2(VB-1)
= 1/40×10-6×1
= 25 KΩ
So, we have
Drain voltage
Therefore,
and
So, the MOSFET is in the saturation region. Therefore, drain current is
ID = 1/2 Kn(VGS - VT)2 (Rest part i.e. 1 + λVDS is neglected as mentioned in question)
2ID = Kn (VB-1)2
Differentiating both side with respect to ID
2 = Kn 2(VB-1)(dVB/dID)
Since,
(at D.C. Voltage) Hence, to get small signal resistance
dVB/dID = 2/Kn 2(VB-1)
= 1/40×10-6×1
= 25 KΩ
Question 89 |
The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the biasing circuits has been omitted for simplicity. For the n -channel MOSFET M. the transconductance gm = 1 mA/V. and body effect and channel length modulation effect are to be neglected. The lower cutoff frequency in Hz of the circuit is approximately at
8 | |
32 | |
50 | |
200 |
Question 89 Explanation:
For the given circuit, we obtain the small signal model as shown in figure below:
Node voltage at V1 as
Output voltage V0 is obtained as
Transfer function is
Pole at
It gives the lower cutoff frequency of transfer function.
i.e.,
or,
Node voltage at V1 as
Output voltage V0 is obtained as
Transfer function is
Pole at
It gives the lower cutoff frequency of transfer function.
i.e.,
or,
Question 90 |
In the circuit shown below the op-amps are ideal. Then Vout in volts is
4 | |
6 | |
8 | |
10 |
Question 90 Explanation:
Question 91 |
A voltage 1000 sin ωt Volts is applied across YZ. Assuming ideal diodes, the voltage measured across WX in Volts, is
sin ωt | |
(sin ωt + |sin ω t|)/2 | |
(sin ωt – |sin ω t|)/2 | |
0 for all t |
Question 91 Explanation:
Question 92 |
The current ib through the base of a silicon npn transistor is 1 + 0.1 cos(10000 πt) mA. At 300 K, the rπ in the small signal model of the transistor is
250 Ω | |
27.5 Ω | |
25 Ω | |
22.5 Ω |
Question 92 Explanation:
Given : ib = 1 + 0.1 cos(10000 πt ) mA
We know that
Where lb is d.c. current through base so
Ib = 1mA
VT = 25mV at room temperature
So,
We know that
Where lb is d.c. current through base so
Ib = 1mA
VT = 25mV at room temperature
So,
Question 93 |
The diodes and capacitors in the circuit shown are ideal. The voltage v(t) across the diode D1 in steady state is
 | |
 | |
 | |
 |
Question 93 Explanation:
C1 will be charged to maximum value of input that is 1 V.
So,
according to KVL.Question 94 |
In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if
Vin< 1.875 V | |
1.875 V < Vin< 3.125 V | |
Vin> 3.125 V | |
0 |
Question 94 Explanation:
For PMOS VSG = VS - VG = 5 - Vin
For PMOS to be ON
So Vin must be less than 4V for MOS to be in linear regions so option C and D are rejected. Now we know that for small Vin output is high and PMOS is in linear region and NMOS is in cutoff region. Similarly for high Vin PMOS is in cutoff and NMOS is in linear region and for Vin in between both are in saturation. So PMOS will be in linear region for Vin < 1.875 V.
For PMOS to be ON
So Vin must be less than 4V for MOS to be in linear regions so option C and D are rejected. Now we know that for small Vin output is high and PMOS is in linear region and NMOS is in cutoff region. Similarly for high Vin PMOS is in cutoff and NMOS is in linear region and for Vin in between both are in saturation. So PMOS will be in linear region for Vin < 1.875 V.
Question 95 |
The circuit shown is a
Low pass filter with  | |
High pass filters with  | |
Low pass filter with  | |
High pass filter with  |
Question 95 Explanation:
T(s) = 
T(s) =
It is the transfer function of high pass filter with cutoff frequency → ω =
rad/sec
T(s) =
It is the transfer function of high pass filter with cutoff frequency → ω =
rad/secQuestion 96 |
The voltage gain Av of the circuit shown below is
 | |
 | |
 | |
 |
Question 96 Explanation:
Apply Miller's theorem to 100 k resistor
Question 97 |
For the same network, with 6 V dc connected at port A, 1 Ω connected at port B draws 7/3A. If 8 V dc is connected to port A. the open circuit voltage at port B is
6 V | |
7 V | |
8 V | |
9 V |
Question 97 Explanation:
Question 98 |
A DC series motor is driven by a chopper circuit. The supply voltage is 220 V and the duty cycle is 25%. Determine the DC voltage applied to the motor
165 V | |
55 V | |
220 V | |
110 V |
Question 98 Explanation:
The Correct Answer Among All the Options is B
Here we have to find out the value of DC voltage that is being applied to the motor.
Given=> Vin=220V, Duty cycle=25%
Now, for a chopper circuit, we have:
Average output voltage=Duty cycle x Supply voltage=> (25/100) x (220)=>55. So, option (b) is the correct option.
Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits
Here we have to find out the value of DC voltage that is being applied to the motor.
Given=> Vin=220V, Duty cycle=25%
Now, for a chopper circuit, we have:
Average output voltage=Duty cycle x Supply voltage=> (25/100) x (220)=>55. So, option (b) is the correct option.
Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits
Question 99 |
A single-phase full-wave AC phase controller feeds power to a resistive load of 100
from a 220 V, 50 Hz supply. What will be the R.M.S. output voltage at delay angles a1= a2 = a = 
/2 of both transistors?
from a 220 V, 50 Hz supply. What will be the R.M.S. output voltage at delay angles a1= a2 = a = /2 of both transistors?  V | |
 V | |
 x 220 V | |
 x 220 V |
Question 99 Explanation:
The Correct Answer Among All the Options is A
Here we have to find the RMS output voltage at delay angles a1=a2=a=ᴨ/2
Now, we have a single phase full wave AC phase controller. We know the formula for Vout(Mean square value) for a AC phase controller . It is given as:
Vout(mean square)= Vm/
[(ᴨα)+sin2α/2](1/2)
Here, it is already given in question that Vm=220V=> 220
, and α=ᴨ/2
So, putting all these values in Vout formula, we will get answer as option (a)
Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits
Here we have to find the RMS output voltage at delay angles a1=a2=a=ᴨ/2
Now, we have a single phase full wave AC phase controller. We know the formula for Vout(Mean square value) for a AC phase controller . It is given as:
Vout(mean square)= Vm/
[(ᴨα)+sin2α/2](1/2) Here, it is already given in question that Vm=220V=> 220
, and α=ᴨ/2 So, putting all these values in Vout formula, we will get answer as option (a)
Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits
Question 100 |
The components of full-wave voltage doubler circuit are
2 diodes and 1 capacitor | |
4 diodes and 1 capacitor | |
2 diodes and 2 capacitor | |
4 diodes and 2 capacitor |
Question 100 Explanation:
As its name suggests, a Voltage Doubler is a voltage multiplier circuit which has a voltage multiplication factor of two. The circuit consists of only two diodes, two capacitors and an oscillating AC input voltage (a PWM waveform could also be used). This simple diode-capacitor pump circuit gives a DC output voltage equal to the peak-to-peak value of the sinusoidal input. In other words, double the peak voltage value because the diodes and the capacitors work together to effectively double the voltage.
Refer : https://www.electronics-tutorials.ws/voltage-multiplier-circuit.html
Refer : https://www.electronics-tutorials.ws/voltage-multiplier-circuit.html
Question 101 |
An amplifier has a signal input voltage Vi of 0.25 V and draws 1 mA from the source. If the amplifier delivers 8 V to a load of 10 mA, the power gain is
340 | |
320 | |
250 | |
150 |
Question 101 Explanation:
Question 102 |
Three amplifiers of gain
are connected in tandem. The feedback loop is closed through a positive gain of 0.008:
The magnitude of A0 for the system to be oscillatory will be
are connected in tandem. The feedback loop is closed through a positive gain of 0.008:
The magnitude of A0 for the system to be oscillatory will be
0.2 | |
0.1 | |
5.0 | |
10.0 |
Question 102 Explanation:
As three amplifiers are cascaded overall gain will be,
Question 103 |
For 555 astable multivibrator, if C = 0.01 μF, RA = 10 kΩ, RB = 50 kΩ, the frequency and the duty cycle will be nearly
1.6 kHz and 54.5% | |
1.3 kHz and 54.5% | |
1.6 KHz and 46.5% | |
1.3 kHz and 46.5% |
Question 103 Explanation:
Question 104 |
The two advantages of FIR filters over IIR- filters are.
they are guaranteed to be stable and non-linear | |
they are marginally stable and linear. | |
they are guaranteed to be stable and may be constrained to have linear phase | |
they are marginally stable and non-linear |
Question 104 Explanation:
IIR filters are recursive and FIR filters are non-recursive. Also FIR filters are linear phase and IIR filters are not; several applications are sensitive to non-linear phase (communications, medical, etc). In implementation, IIR filters require fewer taps (smaller order) and thusly are easier to implement and have fewer zeros. Also FIR filters are always stable, while IIR filters can often become unstable in implementation.
Digital filters with finite-duration impulse response (all-zero, or FIR filters) have both advantages and disadvantages compared to infinite-duration impulse response (IIR) filters.
FIR filters have the following primary advantages:
FIR filters have the following primary advantages:
- They can have exactly linear phase.
- They are always stable.
- The design methods are generally linear.
- They can be realized efficiently in hardware.
- The filter startup transients have finite duration.
Question 105 |
Determine the change in collector. 
due to change in base emitter voltage VBE from 250 C to 1000 C for a Silicon Transistor in Fixed Bias Configuration having 
=100.
(Consider follwing variatio in Silicon transistor parameters with temperature- At T=250C, VBE = 0.65 V and At T = 1000C. VBE = 0.5 V)
due to change in base emitter voltage VBE from 250 C to 1000 C for a Silicon Transistor in Fixed Bias Configuration having =100. (Consider follwing variatio in Silicon transistor parameters with temperature- At T=250C, VBE = 0.65 V and At T = 1000C. VBE = 0.5 V)
 | |
 | |
 | |
 |
Question 105 Explanation:
The Correct Answer Among All the Options is A
Change in collector current w.r.t temperature (T)
=
As only
is changing with temperature, remaining all are constant.
Therefore,
=
= 0.5-0.65
= -0 .15
Given,
After Putting all values in the equation and we get,
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Change in collector current w.r.t temperature (T)
= As only
is changing with temperature, remaining all are constant. Therefore,
= = 0.5-0.65 = -0 .15
Given,
After Putting all values in the equation and we get,
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Question 106 |
Identify A and B current limiting techniques in a.c to d.c power supplies respectively, in the grapgh below.
Current limiting Mode, Constant Current Mode | |
Re-entrant limiting Mode, Current limiting Mode | |
Current limiting Mode, Fold back limiting Mode | |
Fold back limiting Mode, Re-entrant limiting Mode |
Question 106 Explanation:
The Correct Answer Among All the Options is B
Fold-Back Current Limiting:When this method is employed if an overload condition exists, the output voltage and current reduce to safe levels. As can be seen from the following curve, should an overload occur the supply will provide current up its current limit point (aka ‘knee’), and then the output current will fold-back to a lower value as the output voltage reduces towards zero.
This technique is employed in linear power supplies because it reduces the strain on the supply’s internal power devices to minimum. One drawback of fold-back current limiting is that if the supply turns on into a heavy capacitive load, it could latch-up at a reduced current before reaching its full output voltage. Depending upon the design, recovery from a fold-back current limit condition can be automatic, or after a built-in time delay when the overload condition is removed.
Constant Current Limiting : In this method, should an overload occur, the output current stays at its limit point and the output voltage reduces towards zero in a somewhat linear fashion. This technique is used in many switch mode power supply designs. Typically, the supply will automatically return to its normal output voltage when the overload condition is no longer present.
Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits
Fold-Back Current Limiting:When this method is employed if an overload condition exists, the output voltage and current reduce to safe levels. As can be seen from the following curve, should an overload occur the supply will provide current up its current limit point (aka ‘knee’), and then the output current will fold-back to a lower value as the output voltage reduces towards zero.
This technique is employed in linear power supplies because it reduces the strain on the supply’s internal power devices to minimum. One drawback of fold-back current limiting is that if the supply turns on into a heavy capacitive load, it could latch-up at a reduced current before reaching its full output voltage. Depending upon the design, recovery from a fold-back current limit condition can be automatic, or after a built-in time delay when the overload condition is removed.
Constant Current Limiting : In this method, should an overload occur, the output current stays at its limit point and the output voltage reduces towards zero in a somewhat linear fashion. This technique is used in many switch mode power supply designs. Typically, the supply will automatically return to its normal output voltage when the overload condition is no longer present.
Refer the Topic Wise Question for Ripple Removal and Regulation Analog Circuits
Question 107 |
Determine output voltage ‘V0’ for below circuit whre Vin = Sin (100 
t)
t) 2 Sin (100  t) | |
Sin (100  t) | |
Sin (200  t) | |
0.5 Sin (100  t) |
Question 107 Explanation:
The Correct Answer Among All the Options is A
from the figure it is clear that it is negative feedback, so voltage at inverting and non-inverting terminal is same .
,
,
and 
Apply nodal analysis at ‘A’ & ‘D’
=0
=0
Put ,
, after solving we get
Sin (100 
t)
Refer the Topic Wise Question for Op-Amp and Voltage Reference Circuits Analog Circuits
from the figure it is clear that it is negative feedback, so voltage at inverting and non-inverting terminal is same .
, , and Apply nodal analysis at ‘A’ & ‘D’
=0 =0 Put ,
, after solving we get Sin (100 t) Refer the Topic Wise Question for Op-Amp and Voltage Reference Circuits Analog Circuits
Question 108 |
Determine the channel half-width for an n-channel silicon FET having Gate-to-Source voltage, VGS = VP/4, where VP is the Pinch off voltage and drain current, Id = 0. (Consider (a) Donor Concentration ND = 1015 electrons/cm3 (b) Channel half-width for VGS = 0 V is 3
).
). 2.25  | |
3  | |
1.5  | |
0.75  |
Question 108 Explanation:
The Correct Answer Among All the Options is C
Given,
, 
For,
As we know, for ,
→a=b
Here channel width='2'a
Therefore,
=3 →a=3 
For any junction , width(depletion) =w=
=
,
]
…………………….(1)
For n-channel,
w=
w=width of junction i.e. (a-b)
………………………………………………………………(2)
On comparing (1) and (2)
For ,
→b=0 therfore, 
Therefore,
Given ,
→b=1.5
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Given,
, For,
As we know, for ,
→a=b Here channel width='2'a
Therefore,
=3 →a=3 For any junction , width(depletion) =w=
=
, ] …………………….(1) For n-channel,
w=
w=width of junction i.e. (a-b)
………………………………………………………………(2) On comparing (1) and (2)
For ,
→b=0 therfore, Therefore,
Given ,
→b=1.5 Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Question 109 |
A resistor R1 = 4K
is connected across the secondary of transformer for which L1 = 0.2H, 250V Peak voltage at 400 rad/sec is applied to primary winding of transformer.
is connected across the secondary of transformer for which L1 = 0.2H, 250V Peak voltage at 400 rad/sec is applied to primary winding of transformer. 353.55 V | |
500 V | |
882.3 V | |
1000 V |
Question 109 Explanation:
The Correct Answer Among All the Options is C
W= 400rad/sec
Mutual coupling (M)= K
= 0.5
= 0.5
Transformer equation :
+ 0
250
= (0.2)
…………………………………………………………………………(1)
For secondary,
0.5
Peak value across R
0.5
=882.33V
Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits
W= 400rad/sec
Mutual coupling (M)= K
= 0.5
= 0.5
Transformer equation :
+ 0 250
= (0.2) …………………………………………………………………………(1) For secondary,
0.5 Peak value across R
0.5 =882.33V
Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits
Question 110 |
What will be the voltage reading of DC Volmeter placed across the terminals of the Diode in the circuit below,
Having the following periodical input signal ‘Vi (t)’
(Assume cut-in voltage of the Diode = 0 V; Forward resistance of the Diode = 2
)
Having the following periodical input signal ‘Vi (t)’
(Assume cut-in voltage of the Diode = 0 V; Forward resistance of the Diode = 2
) 1.25 V | |
2.5 V | |
0 V | |
0.1 V |
Question 110 Explanation:
The Correct Answer Among All the Options is B
Multimeter always reads average value of a signal in DC mode.
Graph for
Cut in voltage of diode =0V
Forward resistance (
) = 2
.
For positive half cycle ,D1 is forward biased and it can be replaced by its resistance.
Voltage across 2
is 
=
=
But multimeter is connected in reverse , so voltage in multimeter (
)= 
=
=-0.4V
i.e. waveform for multimeter becomes,
For
(-ve half cycle), diode is in off state because it is reversed biased. Therefore circuit becomes
= -
So, complete
will be:
Average value =
=
=
= 2.5V
Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits
Multimeter always reads average value of a signal in DC mode.
Graph for
Cut in voltage of diode =0V
Forward resistance (
) = 2. For positive half cycle ,D1 is forward biased and it can be replaced by its resistance.
Voltage across 2
is = = But multimeter is connected in reverse , so voltage in multimeter (
)= =
=-0.4V i.e. waveform for multimeter becomes,
For
(-ve half cycle), diode is in off state because it is reversed biased. Therefore circuit becomes = - So, complete
will be: Average value =
=
=
= 2.5V
Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits
Question 111 |
If the transformer and diodes in the following circuit are idea, Find out the Capacitor (Co) provides 5% ripple voltage across RL. (Assume that Sin-1(0.95) 
/5 in Radians ln(0.95) -0.051)
/5 in Radians ln(0.95) -0.051) 4.7  F | |
16.7 p F | |
8.7 p | |
2.7 pF |
Question 111 Explanation:
The Correct Answer Among All the Options is C
The figure shown above is a full wave rectifier with a capacitor filter. We have to find the value of the capacitor C0.
Now, capacitor C0= Voltage(Max)/ (2 x freq. x ripple factor x Load resistance)
So, given in question=> Vin=100sin(2ᴨ1000t)
So, now, Voltage(max)=50 volts, Frequency=1000Hz, Ripple factor=2.5 and Load resistance=1000. Putting this value in C0 equation we will get: C0=1 x 10-5F
Nearest value will be equal to option (c)
Refer the Topic Wise Question for Simple Diode and Wave Shaping Circuitsa Analog Circuits
The figure shown above is a full wave rectifier with a capacitor filter. We have to find the value of the capacitor C0.
Now, capacitor C0= Voltage(Max)/ (2 x freq. x ripple factor x Load resistance)
So, given in question=> Vin=100sin(2ᴨ1000t)
So, now, Voltage(max)=50 volts, Frequency=1000Hz, Ripple factor=2.5 and Load resistance=1000. Putting this value in C0 equation we will get: C0=1 x 10-5F
Nearest value will be equal to option (c)
Refer the Topic Wise Question for Simple Diode and Wave Shaping Circuitsa Analog Circuits
Question 112 |
A sinusoidal input which can be reproduced in an OP-AMP without any distortion having slew rate of 10
V/
s and 5V peak output amplitude, has the maximum frequency of
V/s and 5V peak output amplitude, has the maximum frequency of 1KHz. | |
1Hz. | |
31.42KHz. | |
31.42MHz. |
Question 112 Explanation:
The Correct Answer Among All the Options is B
Given=> Slew rate= 10ᴨV/ µs, and Vout(peak)=5V
We have to find out the maximum frequency.
So, slew rate is generally given as the rate of change of output voltage with respect to time.
So slew rate= |dV0/dt|max
Here, slew rate=10ᴨV/ µs, and V0(max)=5V
Also, Output Vout= Amax *w*sin2ᴨfmaxt
So, Vout is also changing with time.
So, we can write: 10ᴨV/ µs= 5(2ᴨ)fmax(Max Value)
On solving this we get: fmax= 1 Hz
Refer the Topic Wise Question for Op-Amp and Voltage Reference Circuits Analog Circuits
Given=> Slew rate= 10ᴨV/ µs, and Vout(peak)=5V
We have to find out the maximum frequency.
So, slew rate is generally given as the rate of change of output voltage with respect to time.
So slew rate= |dV0/dt|max
Here, slew rate=10ᴨV/ µs, and V0(max)=5V
Also, Output Vout= Amax *w*sin2ᴨfmaxt
So, Vout is also changing with time.
So, we can write: 10ᴨV/ µs= 5(2ᴨ)fmax(Max Value)
On solving this we get: fmax= 1 Hz
Refer the Topic Wise Question for Op-Amp and Voltage Reference Circuits Analog Circuits
Question 113 |
Which of the following is NOT a characteristic of Schottky Diode?
Thermionic emission of carriers across Schottky barrier | |
Current conduction in Schottky diodes is by majority carriers | |
Switching speed of Schottky diodes is less compared to p-n junction diodes | |
Schottky diode comprises of Metal-Semiconductor junction |
Question 113 Explanation:
The Correct Answer Among All the Options is C
Schottkey diode has a faster switching speed because of negligible reverse recovery time. This results in a little reverse current overshoot as well. Since no re-combination is required due to the use of majority carriers, switching in schottkey diode is much faster than p-n diodes whose switching speed is limited by the recombination time of minority carriers.
Refer the Topic Wise Question for Simple Diode and Wave Shaping Circuitsa Analog Circuits
Schottkey diode has a faster switching speed because of negligible reverse recovery time. This results in a little reverse current overshoot as well. Since no re-combination is required due to the use of majority carriers, switching in schottkey diode is much faster than p-n diodes whose switching speed is limited by the recombination time of minority carriers.
Refer the Topic Wise Question for Simple Diode and Wave Shaping Circuitsa Analog Circuits
Question 114 |
The ramp signal (Vt: 0 to 5V) is compared with the Soft-Start Signal provided byN- channel MOSPET (Q1) for Amplifier (A1) output. If Q1having low threshold voltage of 0.7 V and negligible ON resistance. 100 p Sec?
What is the duty of output signal of comparator (C1) after 100
sec?
What is the duty of output signal of comparator (C1) after 100
sec? 17.4% | |
34.8 % | |
0% | |
50% |
Question 114 Explanation:
The Correct Answer Among All the Options is B
Here we have to determine the duty of output of Comparator C1. For determining this, we have to determine Vt.
Now, here a ramp signal is given at Vt. So, for Vt= 5/T
Now, duty cycle= PW/T, where PW=Ton - T=> 'T' being the total time.
So, for finding the duty cycle, we have to find both Ton and T.
Both can be found out by considering gate voltage of N-channel MOSFET.
For the N-channel MOSFET=> Gate voltage VG can be determined as: VG= Vdc(1-e-t/т)
Now Vt=0.7volt, and Vt>VG[Vt is having a ramp signal]
So, we can write: 0.7=5volt(1-
)
On solving we will get, t=0.000015sec=15 µsec
So, we have got 't'. Now, we have to determine the output of the first Op-amp. Now,
let the output be Vout1
The only way to determine Vout1 is by applying KCL. Before applying, let us take the voltage at the inverting terminal of the first op-amp as Va and that of non-inverting terminal as Vb
So we can write:
(2.5/3.3) +(2.5-5.5/3) +(2.5 - Vout1/10)=0[By virtual ground property]
On solving this, we will get Vout1= 1.7 Volt.
We have already seen that
Vt= 5/T=> 5 t/T.So, from this we can write: t= Vt x T/5. Now, Vt=Vout1=1.7 volt. So, t= 0.000035seconds=35 µseconds.
So, now Ton= (100+35)=135 µsec, and therefore, we will get duty cycle as: Ton-T/100=35%
(given in options)
Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits
Here we have to determine the duty of output of Comparator C1. For determining this, we have to determine Vt.
Now, here a ramp signal is given at Vt. So, for Vt= 5/T
Now, duty cycle= PW/T, where PW=Ton - T=> 'T' being the total time.
So, for finding the duty cycle, we have to find both Ton and T.
Both can be found out by considering gate voltage of N-channel MOSFET.
For the N-channel MOSFET=> Gate voltage VG can be determined as: VG= Vdc(1-e-t/т)
Now Vt=0.7volt, and Vt>VG[Vt is having a ramp signal]
So, we can write: 0.7=5volt(1-
) On solving we will get, t=0.000015sec=15 µsec
So, we have got 't'. Now, we have to determine the output of the first Op-amp. Now,
let the output be Vout1
The only way to determine Vout1 is by applying KCL. Before applying, let us take the voltage at the inverting terminal of the first op-amp as Va and that of non-inverting terminal as Vb
So we can write:
(2.5/3.3) +(2.5-5.5/3) +(2.5 - Vout1/10)=0[By virtual ground property]
On solving this, we will get Vout1= 1.7 Volt.
We have already seen that
Vt= 5/T=> 5 t/T.So, from this we can write: t= Vt x T/5. Now, Vt=Vout1=1.7 volt. So, t= 0.000035seconds=35 µseconds.
So, now Ton= (100+35)=135 µsec, and therefore, we will get duty cycle as: Ton-T/100=35%
(given in options) Refer the Topic Wise Question for Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET Analog Circuits
Question 115 |
For the silicon transistor shown in the figure below, the value of IB is?
26.47  A | |
52.94  A | |
13.235  A | |
30.11  A |
Question 115 Explanation:
The Correct Answer Among All the Options is D
Given=> A BJT=> Silicon=> VBE=0.7V
ß=100, RE=2.4KΩ, RB=1.9KΩ, Vcc=10v and VEE=-8V
We have to determine=> 'IB' value.
Now, IB= Ic/ß
Applying KVL in base emitter side:
VBE+IERE+VEE=0=> IE= (-VEE-VBE)/RE
On putting the values given in question, we get: IE= 3.041mA
Now, IB= IE/(1+ß)=> 30.11 µA
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
Given=> A BJT=> Silicon=> VBE=0.7V
ß=100, RE=2.4KΩ, RB=1.9KΩ, Vcc=10v and VEE=-8V
We have to determine=> 'IB' value.
Now, IB= Ic/ß
Applying KVL in base emitter side:
VBE+IERE+VEE=0=> IE= (-VEE-VBE)/RE
On putting the values given in question, we get: IE= 3.041mA
Now, IB= IE/(1+ß)=> 30.11 µA
Refer the Topic Wise Question for Single-Stage BJT and MOSFET Amplifiers Analog Circuits
There are 115 questions to complete.